From patchwork Wed Jul 18 10:54:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 10533691 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6053E600F4 for ; Thu, 19 Jul 2018 07:04:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4E44229651 for ; Thu, 19 Jul 2018 07:04:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 39AC12968D; Thu, 19 Jul 2018 07:04:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DF2CF2968E for ; Thu, 19 Jul 2018 07:04:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6BDC56ECDB; Thu, 19 Jul 2018 07:03:46 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4894C6EAC6 for ; Wed, 18 Jul 2018 10:56:40 +0000 (UTC) Received: by mail-pg1-x541.google.com with SMTP id f1-v6so1827142pgq.12 for ; Wed, 18 Jul 2018 03:56:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yvkcdyq+XH9acvZSAOuqu6Z0+SAMtHko9BM9Dtyh8Ho=; b=IUOet3d/VAmp+HnSxpAV5NNDRE6HteowCpYQ3YmICAM8io56wKGYJjf41r9jSeiOsJ nVuLSWOa/5jLBiY5wUMT3223NoIhWmFMz9utIBmDyOHORXt1NPeG6+FZ0Pjlyo+JJ8Q+ /BNfPjVodtcKMEEnuTmwQFlxWiXjWwABnyCqmNQ4t9ztO6OEVWVMncdcVtFdIUq9nx+M gTeYFv4IESPkFWNLFUDZ5ty+O8OsId2d0yiQO5/8dWH5QsS9PCrv7+mQV0itS6vklwE9 0tLjPIsh27rOapRm7WAHlsJrKI7ByTGAsRFrzawsA7xL0O8MnBSaAHS+wJ9Pm8nfxxkA rf6g== X-Gm-Message-State: AOUpUlEnhnoMUaB4YSn9AYbmvHBbGE/tKTvyHzMlhHT/4Ns1DHIHVxLb wp7yg8pee9p4KzvaKJpCHUV3/A== X-Google-Smtp-Source: AAOMgpeJid+L+kbkjCf9l3tbW3BSS/3z5F3/osPfw0sIXap/IYj2q/6XKPsHht6CcSTVz+RhCM3Hpg== X-Received: by 2002:a62:34c4:: with SMTP id b187-v6mr4656608pfa.15.1531911399855; Wed, 18 Jul 2018 03:56:39 -0700 (PDT) Received: from localhost.localdomain ([183.82.229.107]) by smtp.gmail.com with ESMTPSA id x25-v6sm4644452pgv.63.2018.07.18.03.56.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Jul 2018 03:56:39 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel@lists.freedesktop.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Michael Trimarchi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v3 12/18] drm: sun4i: add support for HVCC regulator for DWC HDMI glue Date: Wed, 18 Jul 2018 16:24:52 +0530 Message-Id: <20180718105458.22304-13-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180718105458.22304-1-jagan@amarulasolutions.com> References: <20180718105458.22304-1-jagan@amarulasolutions.com> X-Mailman-Approved-At: Thu, 19 Jul 2018 07:03:42 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jagan Teki MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Icenowy Zheng Allwinner SoCs with DWC HDMI controller have a "HVCC" power pin for the HDMI part, and on some boards it's connected to a dedicated regulator rather than the main 3.3v. Add support for optional HVCC regulator. For boards that doesn't use a dedicated regulator to power it, the default dummy regulator is used. Signed-off-by: Icenowy Zheng Signed-off-by: Jagan Teki --- Changes for v3, v2: - none drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 ++++++++++++++ drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c index 31875b636434..68623a6ac44e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c @@ -113,6 +113,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, if (encoder->possible_crtcs == 0) return -EPROBE_DEFER; + hdmi->vcc_hdmi = devm_regulator_get(dev, "hvcc"); + if (IS_ERR(hdmi->vcc_hdmi)) { + dev_err(dev, "Could not get HDMI power supply\n"); + return PTR_ERR(hdmi->vcc_hdmi); + } + hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl"); if (IS_ERR(hdmi->rst_ctrl)) { dev_err(dev, "Could not get ctrl reset control\n"); @@ -131,6 +137,12 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, return ret; } + ret = regulator_enable(hdmi->vcc_hdmi); + if (ret) { + dev_err(dev, "Cannot enable HDMI power supply\n"); + goto err_disable_vcc; + } + ret = clk_prepare_enable(hdmi->clk_tmds); if (ret) { dev_err(dev, "Could not enable tmds clock\n"); @@ -183,6 +195,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, clk_disable_unprepare(hdmi->clk_tmds); err_assert_ctrl_reset: reset_control_assert(hdmi->rst_ctrl); +err_disable_vcc: + regulator_disable(hdmi->vcc_hdmi); return ret; } diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h index aadbe0a10b0c..af34c498295e 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000 @@ -176,6 +177,7 @@ struct sun8i_dw_hdmi { struct drm_encoder encoder; struct sun8i_hdmi_phy *phy; struct dw_hdmi_plat_data plat_data; + struct regulator *vcc_hdmi; struct reset_control *rst_ctrl; };