From patchwork Tue Sep 4 00:57:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilia Mirkin X-Patchwork-Id: 10586427 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AB40B14BD for ; Tue, 4 Sep 2018 00:58:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9990628FB1 for ; Tue, 4 Sep 2018 00:58:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8DEFB28FB4; Tue, 4 Sep 2018 00:58:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 343F728FB1 for ; Tue, 4 Sep 2018 00:58:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 395B06E2F4; Tue, 4 Sep 2018 00:57:53 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qk1-x742.google.com (mail-qk1-x742.google.com [IPv6:2607:f8b0:4864:20::742]) by gabe.freedesktop.org (Postfix) with ESMTPS id D93C689DA4; Tue, 4 Sep 2018 00:57:50 +0000 (UTC) Received: by mail-qk1-x742.google.com with SMTP id f17-v6so1360894qkh.4; Mon, 03 Sep 2018 17:57:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=m6zpOU2F5KfatNehn+11PsgJRuEkUFcKRjqqjY8G0Gs=; b=dXmgopT2t+N1X/lfW7zeZz5PilG98xpDHvlvhBjMejn9Uir7gtMDYv4pmeiA6LJXEO 0llI//vpZIjA6Ocl4neFDQ+TEwbVy9J2mbWDk8HnCIZdPZZVWhmq83Upkue/7WmNiqoz pLe0Vg99dUW8F5j6Z1Cn7aECGC47Eou4vLK4mCMKdLFyoWNFQ5Fs+0QoOOhiWhbiju5w 2tKFMZKysIKfZQacjSWQzFVt8ALRM4SSpo0UXeZ+QBH8aHXODyH1oXKae4pKCegrbWBi n66ClJspugsrIHFhcKu1szj6P5XlePt2xcDo5YWC/ti88GyNlebUBxFzqfpAzvLKadrZ UlXQ== X-Gm-Message-State: APzg51A4tS9QavxI+9SyP+Fs46O2zNBbFH7pHUOoAfAG+9EICd2RqqHd W9Wcc9NDbhGdFGbnEd53KKZ+LEkQ X-Google-Smtp-Source: ANB0VdYhqLU09t0dgH1WILp6VIxobAIgx12sFQQz3afDa/ztKEvoRGym4w6s2wOXGc+2dZHGhTIuKg== X-Received: by 2002:a37:a54f:: with SMTP id o76-v6mr26213375qke.125.1536022669914; Mon, 03 Sep 2018 17:57:49 -0700 (PDT) Received: from athos.fios-router.home (pool-108-29-13-48.nycmny.fios.verizon.net. [108.29.13.48]) by smtp.gmail.com with ESMTPSA id o68-v6sm9779960qkf.9.2018.09.03.17.57.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Sep 2018 17:57:49 -0700 (PDT) From: Ilia Mirkin To: Ben Skeggs , nouveau@lists.freedesktop.org Subject: [PATCH 4/5] drm/nouveau/disp: add support for setting scdc parameters for high modes Date: Mon, 3 Sep 2018 20:57:36 -0400 Message-Id: <20180904005737.5346-5-imirkin@alum.mit.edu> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20180904005737.5346-1-imirkin@alum.mit.edu> References: <20180904005737.5346-1-imirkin@alum.mit.edu> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP When SCDC is supported, make sure that we configure the GPU and monitor to the same parameters. Signed-off-by: Ilia Mirkin --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 40 ++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 9bae4db84cfb..77cf5878896e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -506,6 +507,7 @@ nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) static void nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) { + struct nouveau_drm *drm = nouveau_drm(encoder->dev); struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); struct nv50_disp *disp = nv50_disp(encoder->dev); @@ -523,9 +525,12 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) .pwr.rekey = 56, /* binary driver, and tegra, constant */ }; struct nouveau_connector *nv_connector; + struct drm_hdmi_info *hdmi; u32 max_ac_packet; union hdmi_infoframe avi_frame; union hdmi_infoframe vendor_frame; + bool scdc_supported, high_tmds_clock_ratio = false, scrambling = false; + u8 config; int ret; int size; @@ -533,8 +538,11 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) if (!drm_detect_hdmi_monitor(nv_connector->edid)) return; + hdmi = &nv_connector->base.display_info.hdmi; + scdc_supported = hdmi->scdc.supported; + ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame.avi, mode, - false); + scdc_supported); if (!ret) { /* We have an AVI InfoFrame, populate it to the display */ args.pwr.avi_infoframe_length @@ -557,12 +565,42 @@ nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) max_ac_packet -= 18; /* constant from tegra */ args.pwr.max_ac_packet = max_ac_packet / 32; + if (hdmi->scdc.scrambling.supported) { + high_tmds_clock_ratio = mode->clock > 340000; + scrambling = high_tmds_clock_ratio || + hdmi->scdc.scrambling.low_rates; + } + + args.pwr.scdc = + NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE * scrambling | + NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 * high_tmds_clock_ratio; + size = sizeof(args.base) + sizeof(args.pwr) + args.pwr.avi_infoframe_length + args.pwr.vendor_infoframe_length; nvif_mthd(&disp->disp->object, 0, &args, size); + nv50_audio_enable(encoder, mode); + + /* If SCDC is supported by the downstream monitor, update + * divider / scrambling settings to what we programmed above. + */ + if (!hdmi->scdc.scrambling.supported) + return; + + ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &config); + if (ret < 0) { + NV_ERROR(drm, "Failure to read SCDC_TMDS_CONFIG: %d\n", ret); + return; + } + config &= ~(SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE); + config |= SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 * high_tmds_clock_ratio; + config |= SCDC_SCRAMBLING_ENABLE * scrambling; + ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, config); + if (ret < 0) + NV_ERROR(drm, "Failure to write SCDC_TMDS_CONFIG = 0x%02x: %d\n", + config, ret); } /******************************************************************************