| Message ID | 20180904044053.15425-3-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: allwinner: Add A64 DE2 HDMI support | expand |
On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote: > Video PLLs on A64 can be set to higher rate that it is actually > supported by HW. > > Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP > clock driver. Interestengly, user manual specifies maximum frequency to > be 600 MHz. Historically, this data was wrong in some user manuals for > other SoCs, so more faith is put in BSP clock driver. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Applied, thanks! Maxime
Hi, On 09/05/2018 10:16 AM, Maxime Ripard wrote: > On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote: >> Video PLLs on A64 can be set to higher rate that it is actually >> supported by HW. >> >> Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP >> clock driver. Interestengly, user manual specifies maximum frequency to >> be 600 MHz. Historically, this data was wrong in some user manuals for >> other SoCs, so more faith is put in BSP clock driver. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > Applied, thanks! > Maxime > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel what source tree this patch is supposed to apply for ? I can't find the SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX declaration in 4.19 Thank you Sergey <html> <head> <meta http-equiv="Content-Type" content="text/html; charset=windows-1252"> </head> <body text="#000000" bgcolor="#FFFFFF"> Hi,<br> <div class="moz-cite-prefix">On 09/05/2018 10:16 AM, Maxime Ripard wrote:<br> </div> <blockquote type="cite" cite="mid:20180905071645.ibhcuq5coc6gl6k3@flea"> <pre wrap="">On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote: </pre> <blockquote type="cite"> <pre wrap="">Video PLLs on A64 can be set to higher rate that it is actually supported by HW. Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP clock driver. Interestengly, user manual specifies maximum frequency to be 600 MHz. Historically, this data was wrong in some user manuals for other SoCs, so more faith is put in BSP clock driver. Signed-off-by: Icenowy Zheng <a class="moz-txt-link-rfc2396E" href="mailto:icenowy@aosc.io"><icenowy@aosc.io></a> </pre> </blockquote> <pre wrap=""> Applied, thanks! Maxime </pre> <br> <fieldset class="mimeAttachmentHeader"></fieldset> <br> <pre wrap="">_______________________________________________ linux-arm-kernel mailing list <a class="moz-txt-link-abbreviated" href="mailto:linux-arm-kernel@lists.infradead.org">linux-arm-kernel@lists.infradead.org</a> <a class="moz-txt-link-freetext" href="http://lists.infradead.org/mailman/listinfo/linux-arm-kernel">http://lists.infradead.org/mailman/listinfo/linux-arm-kernel</a> </pre> </blockquote> what source tree this patch is supposed to apply for ?<br> I can't find the SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX declaration in 4.19<br> <br> Thank you<br> Sergey<br> </body> </html>
Hi, On 09/05/2018 10:16 AM, Maxime Ripard wrote: > On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote: >> Video PLLs on A64 can be set to higher rate that it is actually >> supported by HW. >> >> Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP >> clock driver. Interestengly, user manual specifies maximum frequency to >> be 600 MHz. Historically, this data was wrong in some user manuals for >> other SoCs, so more faith is put in BSP clock driver. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > Applied, thanks! > Maxime > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel what source tree this patch is supposed to apply for ? I can't find the SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX declaration in 4.19 Thank you Sergey
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index d0e30192f0cf..5f80eb018014 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -64,18 +64,19 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", BIT(28), /* lock */ CLK_SET_RATE_UNGATE); -static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0", - "osc24M", 0x010, - 192000000, /* Minimum rate */ - 8, 7, /* N */ - 0, 4, /* M */ - BIT(24), /* frac enable */ - BIT(25), /* frac select */ - 270000000, /* frac rate 0 */ - 297000000, /* frac rate 1 */ - BIT(31), /* gate */ - BIT(28), /* lock */ - CLK_SET_RATE_UNGATE); +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", + "osc24M", 0x010, + 192000000, /* Minimum rate */ + 1008000000, /* Maximum rate */ + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", "osc24M", 0x018, @@ -126,18 +127,19 @@ static struct ccu_nk pll_periph1_clk = { }, }; -static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1", - "osc24M", 0x030, - 192000000, /* Minimum rate */ - 8, 7, /* N */ - 0, 4, /* M */ - BIT(24), /* frac enable */ - BIT(25), /* frac select */ - 270000000, /* frac rate 0 */ - 297000000, /* frac rate 1 */ - BIT(31), /* gate */ - BIT(28), /* lock */ - CLK_SET_RATE_UNGATE); +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", + "osc24M", 0x030, + 192000000, /* Minimum rate */ + 1008000000, /* Maximum rate */ + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", "osc24M", 0x038,
Video PLLs on A64 can be set to higher rate that it is actually supported by HW. Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP clock driver. Interestengly, user manual specifies maximum frequency to be 600 MHz. Historically, this data was wrong in some user manuals for other SoCs, so more faith is put in BSP clock driver. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- New patch in v4. drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 50 ++++++++++++++------------- 1 file changed, 26 insertions(+), 24 deletions(-)