From patchwork Tue Sep 18 17:21:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Engestrom X-Patchwork-Id: 10604637 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8505E157B for ; Tue, 18 Sep 2018 17:22:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6B8B82A2A8 for ; Tue, 18 Sep 2018 17:22:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5CCB528C0D; Tue, 18 Sep 2018 17:22:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 05A762B7C0 for ; Tue, 18 Sep 2018 17:22:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E17F96E437; Tue, 18 Sep 2018 17:22:55 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4608B6E435 for ; Tue, 18 Sep 2018 17:22:54 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Sep 2018 10:22:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,390,1531810800"; d="scan'208";a="71005752" Received: from dkiernan-mobl3.ger.corp.intel.com (HELO eengestr-dev.ger.corp.intel.com) ([10.252.16.103]) by fmsmga007.fm.intel.com with ESMTP; 18 Sep 2018 10:22:33 -0700 From: Eric Engestrom To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] drm/fourcc: rename Intel modifiers to follow the naming convention Date: Tue, 18 Sep 2018 18:21:59 +0100 Message-Id: <20180918172217.18754-1-eric.engestrom@intel.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 Organization: Intel Corp UK X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org, Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP All the other vendors use the format DRM_FORMAT_MOD_{SAMSUNG,QCOM,VIVANTE,NVIDIA,BROADCOM,ARM}_* for their modifiers, except Intel. Suggested-by: Gerd Hoffmann Signed-off-by: Eric Engestrom Reviewed-by: Daniel Vetter on both patches. --- include/uapi/drm/drm_fourcc.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 139632b871816f9e3dad..170a562223387687592a 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -271,7 +271,8 @@ extern "C" { * sharing. It exists since on a given platform it does uniquely identify the * layout in a simple way for i915-specific userspace. */ -#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1) +#define DRM_FORMAT_MOD_INTEL_X_TILED fourcc_mod_code(INTEL, 1) +#define I915_FORMAT_MOD_X_TILED DRM_FORMAT_MOD_INTEL_X_TILED /* * Intel Y-tiling layout @@ -286,7 +287,8 @@ extern "C" { * sharing. It exists since on a given platform it does uniquely identify the * layout in a simple way for i915-specific userspace. */ -#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2) +#define DRM_FORMAT_MOD_INTEL_Y_TILED fourcc_mod_code(INTEL, 2) +#define I915_FORMAT_MOD_Y_TILED DRM_FORMAT_MOD_INTEL_Y_TILED /* * Intel Yf-tiling layout @@ -301,7 +303,8 @@ extern "C" { * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width * in pixel depends on the pixel depth. */ -#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3) +#define DRM_FORMAT_MOD_INTEL_Yf_TILED fourcc_mod_code(INTEL, 3) +#define I915_FORMAT_MOD_Yf_TILED DRM_FORMAT_MOD_INTEL_Yf_TILED /* * Intel color control surface (CCS) for render compression @@ -320,8 +323,10 @@ extern "C" { * But that fact is not relevant unless the memory is accessed * directly. */ -#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4) -#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) +#define DRM_FORMAT_MOD_INTEL_Y_TILED_CCS fourcc_mod_code(INTEL, 4) +#define I915_FORMAT_MOD_Y_TILED_CCS DRM_FORMAT_MOD_INTEL_Y_TILED_CCS +#define DRM_FORMAT_MOD_INTEL_Yf_TILED_CCS fourcc_mod_code(INTEL, 5) +#define I915_FORMAT_MOD_Yf_TILED_CCS DRM_FORMAT_MOD_INTEL_Yf_TILED_CCS /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks