From patchwork Tue Sep 25 08:49:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 10615363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6DF2114BD for ; Wed, 26 Sep 2018 07:28:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 55B2C2A3B4 for ; Wed, 26 Sep 2018 07:28:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A3BC2A3BB; Wed, 26 Sep 2018 07:28:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D1C322A3B4 for ; Wed, 26 Sep 2018 07:28:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A4DAE6E3D5; Wed, 26 Sep 2018 07:28:44 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by gabe.freedesktop.org (Postfix) with ESMTPS id 06B2A6E104 for ; Tue, 25 Sep 2018 08:49:54 +0000 (UTC) Received: by mail-pg1-x541.google.com with SMTP id g2-v6so3011867pgu.11 for ; Tue, 25 Sep 2018 01:49:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=QA1xJbsShDdVjIaCDPv07Gd9rn3MI9CCJi3SGgUTdD0=; b=KIpmj0i2oa3ABaECk5I/o3wAC3OINndUZYAR4ZsmhkUmbsJ50toC9rpu7UNLh8igXA wwX1mi9ZzHORgj81NS/3oCIFfrHVjWtrtfVpgtdAJk9QNRgEWgRHJ6jnHOLGr4kUVW8l PoH12FlDUflUkuBoYsDXpY/tD12Ds9Ld0yMzc0bFIt8YDutKBD4oMU6m6mpJRprFfjSs DuUA4tzK5IumRcqMhANYsTiifbHG45jtzcHHv9VjRmKWSTnvKcZRDHUuFKB8AFXao7A/ vYY1jF9GvHDJXYpztKpXbyVfH24sK6Y8GtP7lNnogSh76lfzO/oE9Ugx+7ECdX2SICCm yw9Q== X-Gm-Message-State: ABuFfohqeTZFQcvKMeFYlr4jpkFOaI+ITRsyUoaImgLkCdm4ZdNYZmFN fIYRqau6BAL20edcGZcIS2gsUg== X-Google-Smtp-Source: ACcGV606ZonDpIxtCcVeCpRmR09h62ZHojLMi2qsVb+ZdIXhoPbsKYgM1QlXH6k/pQhMgrmRPwc/gw== X-Received: by 2002:a62:3545:: with SMTP id c66-v6mr2521408pfa.63.1537865393466; Tue, 25 Sep 2018 01:49:53 -0700 (PDT) Received: from localhost.localdomain ([27.7.51.1]) by smtp.gmail.com with ESMTPSA id f62-v6sm2184295pfg.74.2018.09.25.01.49.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Sep 2018 01:49:52 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Icenowy Zheng , Vasily Khoruzhick , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v5 1/2] arm64: dts: allwinner: a64: Add display pipeline Date: Tue, 25 Sep 2018 14:19:39 +0530 Message-Id: <20180925084940.27903-1-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 26 Sep 2018 07:27:58 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jagan Teki Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first TCON is connected to LCD and the second is to HDMI. The HDMI controller/PHY pair is similar to the one on H3/H5. Add all required device tree nodes of the display pipeline, including the TCON0 LCD one and the TCON1 HDMI one. Signed-off-by: Jagan Teki [Icenowy: refactor commit message and add 1st pipeline] Signed-off-by: Icenowy Zheng --- Changes for v5: - Use hdmi_phy compatible for A64 Changes for v4: - Misc fixes - Dropped second PLL from HDMI PHY clock Changes for v3.1: - Refactor commit message to make it more clear. - Added first pipeline (mixer0 -> tcon0) Changes for v3: - Squash all pipeline components in one patch - Add status for mixer1 and tcon1 Changes for v2: - Change compatibles and other based on previous patch changes arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 166 ++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index e4cfa8778623..f3a66f888205 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -121,6 +121,13 @@ }; }; + de: display-engine { + compatible = "allwinner,sun50i-a64-display-engine"; + allwinner,pipelines = <&mixer0>, + <&mixer1>; + status = "disabled"; + }; + osc24M: osc24M_clk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -203,6 +210,52 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + mixer0: mixer@100000 { + compatible = "allwinner,sun50i-a64-de2-mixer-0"; + reg = <0x100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@200000 { + compatible = "allwinner,sun50i-a64-de2-mixer-1"; + reg = <0x200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + + mixer1_out_tcon1: endpoint { + remote-endpoint = <&tcon1_in_mixer1>; + }; + }; + }; + }; }; syscon: syscon@1c00000 { @@ -237,6 +290,75 @@ #dma-cells = <1>; }; + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun50i-a64-tcon-lcd", + "allwinner,sun8i-a83t-tcon-lcd"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; + reset-names = "lcd", "lvds"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + + tcon1: lcd-controller@1c0d000 { + compatible = "allwinner,sun50i-a64-tcon-tv", + "allwinner,sun8i-a83t-tcon-tv"; + reg = <0x01c0d000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON1>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon1_in: port@0 { + reg = <0>; + + tcon1_in_mixer1: endpoint { + remote-endpoint = <&mixer1_out_tcon1>; + }; + }; + + tcon1_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon1_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_tcon1>; + }; + }; + }; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun50i-a64-mmc"; reg = <0x01c0f000 0x1000>; @@ -707,6 +829,50 @@ status = "disabled"; }; + hdmi: hdmi@1ee0000 { + compatible = "allwinner,sun50i-a64-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; + reg-io-width = <1>; + interrupts = ; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, + <&ccu CLK_HDMI>; + clock-names = "iahb", "isfr", "tmds"; + resets = <&ccu RST_BUS_HDMI1>; + reset-names = "ctrl"; + phys = <&hdmi_phy>; + phy-names = "hdmi-phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_tcon1: endpoint { + remote-endpoint = <&tcon1_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_phy: hdmi-phy@1ef0000 { + compatible = "allwinner,sun50i-a64-hdmi-phy"; + reg = <0x01ef0000 0x10000>; + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, + <&ccu 7>; + clock-names = "bus", "mod", "pll-0"; + resets = <&ccu RST_BUS_HDMI0>; + reset-names = "phy"; + #phy-cells = <0>; + }; + rtc: rtc@1f00000 { compatible = "allwinner,sun6i-a31-rtc"; reg = <0x01f00000 0x54>;