From patchwork Mon Oct 8 09:27:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sravanthi Kollukuduru X-Patchwork-Id: 10630287 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8ECB5933 for ; Mon, 8 Oct 2018 09:27:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7EFA628488 for ; Mon, 8 Oct 2018 09:27:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7312E28C11; Mon, 8 Oct 2018 09:27:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0F61728488 for ; Mon, 8 Oct 2018 09:27:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EDC96E107; Mon, 8 Oct 2018 09:27:56 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id A4A9F6E106; Mon, 8 Oct 2018 09:27:54 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4CC7C60C62; Mon, 8 Oct 2018 09:27:53 +0000 (UTC) Received: from skolluku-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: skolluku@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9312D60C7B; Mon, 8 Oct 2018 09:27:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9312D60C7B From: Sravanthi Kollukuduru To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH 2/3] drm/msm/dpu: Integrate interconnect API in MDSS Date: Mon, 8 Oct 2018 14:57:29 +0530 Message-Id: <20181008092730.1199-3-skolluku@codeaurora.org> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20181008092730.1199-1-skolluku@codeaurora.org> References: <20181008092730.1199-1-skolluku@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sean@poorly.run, seanpaul@chromium.org, Sravanthi Kollukuduru MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The interconnect framework is designed to provide a standard kernel interface to control the settings of the interconnects on a SoC. The interconnect API uses a consumer/provider-based model, where the providers are the interconnect buses and the consumers could be various drivers. MDSS is one of the interconnect consumers which uses the interconnect APIs to get the path between endpoints and set its bandwidth/latency/QoS requirements for the given interconnected path. Signed-off-by: Sravanthi Kollukuduru --- drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 56 +++++++++++++++++++++++++++++--- 1 file changed, 52 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c index 2235ef8129f4..8391e5c1e559 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c @@ -4,10 +4,12 @@ */ #include "dpu_kms.h" +#include #define to_dpu_mdss(x) container_of(x, struct dpu_mdss, base) #define HW_INTR_STATUS 0x0010 +#define MAX_AXI_PORT_COUNT 3 struct dpu_mdss { struct msm_mdss base; @@ -16,8 +18,36 @@ struct dpu_mdss { u32 hwversion; struct dss_module_power mp; struct dpu_irq_controller irq_controller; + struct icc_path *path[MAX_AXI_PORT_COUNT]; + u32 num_paths; }; +static int dpu_mdss_parse_data_bus_icc_path( + struct drm_device *dev, struct dpu_mdss *dpu_mdss) +{ + struct icc_path *path0 = of_icc_get(dev->dev, "port0"); + struct icc_path *path1 = of_icc_get(dev->dev, "port1"); + int total_num_paths = 0; + + if (IS_ERR(path0)) + return PTR_ERR(path0); + + dpu_mdss->path[0] = path0; + total_num_paths = 1; + + if (!IS_ERR(path1)) { + dpu_mdss->path[1] = path1; + total_num_paths++; + } + + if (total_num_paths > MAX_AXI_PORT_COUNT) + return -EINVAL; + + dpu_mdss->num_paths = total_num_paths; + + return 0; +} + static irqreturn_t dpu_mdss_irq(int irq, void *arg) { struct dpu_mdss *dpu_mdss = arg; @@ -127,7 +157,12 @@ static int dpu_mdss_enable(struct msm_mdss *mdss) { struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss); struct dss_module_power *mp = &dpu_mdss->mp; - int ret; + int ret, i; + u64 ab = (dpu_mdss->num_paths) ? 6800000000/dpu_mdss->num_paths : 0; + u64 ib = 6800000000; + + for (i = 0; i < dpu_mdss->num_paths; i++) + icc_set(dpu_mdss->path[i], ab, ib); ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, true); if (ret) @@ -140,12 +175,15 @@ static int dpu_mdss_disable(struct msm_mdss *mdss) { struct dpu_mdss *dpu_mdss = to_dpu_mdss(mdss); struct dss_module_power *mp = &dpu_mdss->mp; - int ret; + int ret, i; ret = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false); if (ret) DPU_ERROR("clock disable failed, ret:%d\n", ret); + for (i = 0; i < dpu_mdss->num_paths; i++) + icc_set(dpu_mdss->path[i], 0, 0); + return ret; } @@ -155,6 +193,7 @@ static void dpu_mdss_destroy(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct dpu_mdss *dpu_mdss = to_dpu_mdss(priv->mdss); struct dss_module_power *mp = &dpu_mdss->mp; + int i; _dpu_mdss_irq_domain_fini(dpu_mdss); @@ -163,6 +202,9 @@ static void dpu_mdss_destroy(struct drm_device *dev) msm_dss_put_clk(mp->clk_config, mp->num_clk); devm_kfree(&pdev->dev, mp->clk_config); + for (i = 0; i < dpu_mdss->num_paths; i++) + icc_put(dpu_mdss->path[i]); + if (dpu_mdss->mmio) devm_iounmap(&pdev->dev, dpu_mdss->mmio); dpu_mdss->mmio = NULL; @@ -203,6 +245,12 @@ int dpu_mdss_init(struct drm_device *dev) } dpu_mdss->mmio_len = resource_size(res); + ret = dpu_mdss_parse_data_bus_icc_path(dev, dpu_mdss); + if (ret) { + DPU_ERROR("failed to parse icc path, ret=%d\n", ret); + return ret; + } + mp = &dpu_mdss->mp; ret = msm_dss_parse_clock(pdev, mp); if (ret) { @@ -224,14 +272,14 @@ int dpu_mdss_init(struct drm_device *dev) goto irq_error; } + priv->mdss = &dpu_mdss->base; + pm_runtime_enable(dev->dev); pm_runtime_get_sync(dev->dev); dpu_mdss->hwversion = readl_relaxed(dpu_mdss->mmio); pm_runtime_put_sync(dev->dev); - priv->mdss = &dpu_mdss->base; - return ret; irq_error: