From patchwork Fri Oct 12 16:35:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandru-Cosmin Gheorghe X-Patchwork-Id: 10638863 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 708B7157A for ; Fri, 12 Oct 2018 16:36:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C52E2BEEE for ; Fri, 12 Oct 2018 16:36:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 503502BF8D; Fri, 12 Oct 2018 16:36:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A37E32BF39 for ; Fri, 12 Oct 2018 16:36:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5CC96E4CE; Fri, 12 Oct 2018 16:36:35 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from EUR02-VE1-obe.outbound.protection.outlook.com (mail-ve1eur02on062b.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe06::62b]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB0E66E4CC for ; Fri, 12 Oct 2018 16:36:32 +0000 (UTC) Received: from e114479-lin.cambridge.arm.com (217.140.106.51) by AM5PR0802MB2545.eurprd08.prod.outlook.com (2603:10a6:203:a0::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.24; Fri, 12 Oct 2018 16:36:31 +0000 From: Alexandru Gheorghe To: seanpaul@chromium.org, airlied@linux.ie, dri-devel@lists.freedesktop.org, liviu.dudau@arm.com, brian.starkey@arm.com, malidp@foss.arm.com, gustavo@padovan.org, maarten.lankhorst@linux.intel.com, ayan.halder@arm.com, daniel.vetter@ffwll.ch, raymond.smith@arm.com, david.garbett@arm.com, lisa.wu@arm.com, matt.szczesiak@arm.com, charles.xu@arm.com, james.qian.wang@arm.com Subject: [PATCH v4 7/9] drm/afbc: Add AFBC modifier usage documentation Date: Fri, 12 Oct 2018 17:35:58 +0100 Message-Id: <20181012163600.20331-8-alexandru-cosmin.gheorghe@arm.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181012163600.20331-1-alexandru-cosmin.gheorghe@arm.com> References: <20181012163600.20331-1-alexandru-cosmin.gheorghe@arm.com> MIME-Version: 1.0 X-Originating-IP: [217.140.106.51] X-ClientProxiedBy: CWLP265CA0200.GBRP265.PROD.OUTLOOK.COM (2603:10a6:401:4e::20) To AM5PR0802MB2545.eurprd08.prod.outlook.com (2603:10a6:203:a0::21) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2c8711db-8725-4aad-4428-08d63060ddfc X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020); SRVR:AM5PR0802MB2545; X-Microsoft-Exchange-Diagnostics: 1; AM5PR0802MB2545; 3:j6trgE8Epm9SNLpUc2n5GEgTvN5XPVdYGxL3/Wjm+TlQLRDHyOTfHhmShv9q1r2kGWcBN2ykaa+fl46mISnRlyvdzcwSFdPW3bHr+K/8Lo95NsS/OdtPr+fxS5ALtAK2/2qlbMC+6x3hixIP2YaHQmRI9qntEbFmvgRQGmtdJ/QbONkf0REM6zVVi9ZG2BIa9sntNWs+eXitvgQhc1/8jxhC4E7JReb+HpjlTohQHhBXNqE6XsTsgVUIYB9kIuMd; 25:/RYvtY7XhcpEfkc1UFri1kWtA5yI3nJZJAZYnk2Vpzw4EAG3UX++twtwvCMseiO/erAiTQFzQeY0UHxL7y0SlC2iaeCaWtsiingxOsPE1GgEzG28u/IEFSzYxRhR0QwCJyNJHwP4cmnx40BYjbIyBJR4CogBRDopoLuofk/yn4HN7t3EJZZ1XurX29EwDsXNgSCqJ1GgpJHr1uz+qA6OJerAWRe4/Zt+xKgPbTyK0TJupZlZ1NC1uJBYvv/Nk+u1qiiRMBdJezYlDfCnj09rNu/HRu5h46dpWGiDsXmlYBkNP2nq42Tn2933sp6X/Iqd3fN7hFQmzwbF4LoYyfpmtA==; 31:tnKjd2b1GYxuH0bDWYhZR21U3npSm+q8cb/krW/l/hTNyKmz0W8+rleYk9VVyIwJJjxCS4X8pNYFfsjVLEVRjElFmmlwTXBFWO6T6iddq/5twJ8/8jraNrwpjN0FVlCAGq4nnp9y+wFJxewCoSZYnbFTN2L4GQEkd6EH3vZW9rdsSpGX2PhA+fEz6to/VhofHtbHdhV5eHsaVI9fnjXyWpgqJSELK1zXL8wmRlcJGTQ= X-MS-TrafficTypeDiagnostic: AM5PR0802MB2545: NoDisclaimer: True X-Microsoft-Exchange-Diagnostics: 1; AM5PR0802MB2545; 20:Q76LVMp780LOOnktrhom74SeK/RjbB3A3VAF4YZRzShFQuq52krDSEBv/WJ19yAesYEI/2JyaPkhdVbEFGVCU2NZIBmZ9he6MRPWJnePpHiu+fKTdToDvP9qc4YOUbgXCh7pZRchzXfa49oXjmpj9XuZ8NlV7YJZtp+8HT6GEt2IDfa71Ff3JosBxS6rE6HfxWPMJBsT2/vQrzqVNCbEpw6MgmoIFzZw+/1zpcQugBh/ZP90GVbFcN8+jP5UhMyIJs6hc+77pMUgS48WsoPGmM9wpP/zCAHMjb0iRQfsN8/Um9aVPW6IPESj3gcCRPuUFRNQNmrJ2m1m1c2Pz4Bx17FeFHQOd1dfoyK+vsjK4ai/NpnYHPoLRjis30Tib6VST4JdoYxsHqQvj8RAUD7D/Exvj51ou4qDFe/kKziBSqw=; 4:rBXDBg5VzVHpHDqMvLGO7ga4GPm/fa7iW0CWXCNErpKiQnOMeTYMSLori8ehdhtnBUe8PGtpTQtljS1ImmeEYKmxd8VIRi5Ia7IAVVqQHhRJ7GLHaoKnJMRx8dxk2EDRXr3L2NKlgMCMimHKH5IeQCH/QR2+YWryy8TIKbx4WQgwjOyblRDH+nKukx7+mzT6t3y4MZV+h+w941YFZJBUV3W1ICAtTHTb79GIS2QxoDGyTAfFDea85zyURa85Caes6PgJzRVAG4sAoNrI9ml10D5A+f7kbnajcwvhXkYygQUIzts97NqqYLw5PdVANS+l X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(180628864354917); X-MS-Exchange-SenderADCheck: 1 X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(6055026)(149066)(150057)(6041310)(20161123564045)(20161123562045)(20161123558120)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(201708071742011)(7699051); SRVR:AM5PR0802MB2545; BCL:0; PCL:0; RULEID:; SRVR:AM5PR0802MB2545; X-Forefront-PRVS: 0823A5777B X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(396003)(136003)(39860400002)(346002)(376002)(366004)(199004)(189003)(25786009)(4326008)(81156014)(72206003)(106356001)(105586002)(81166006)(478600001)(5660300001)(47776003)(97736004)(26005)(8936002)(50226002)(66066001)(476003)(16526019)(6486002)(186003)(2906002)(8676002)(316002)(16586007)(7696005)(50466002)(956004)(2616005)(486006)(6666004)(7736002)(305945005)(52116002)(48376002)(68736007)(76176011)(51416003)(86362001)(36756003)(53936002)(386003)(446003)(1076002)(3846002)(6116002)(11346002)(14444005)(6636002)(921003)(1121003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM5PR0802MB2545; H:e114479-lin.cambridge.arm.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; AM5PR0802MB2545; 23:iPlSwF+ESukXYE9bghsKwf0JdWFcZVu5KmDwQ2k?= iAGRK7egasD3P7ZZHltWcyQa3XBZ2DJB7e5I7Ddi2OaXR2ePujzeFkZH+OzhtpJwtxZxAAxsQ3z92C8928qp4tRdrNsGt00D6y5Rt7p4Aca/3xXpCHqiIu6RKOrdjVOosSVKIqufvrqhVZJU3OULgMJ63SBu2c4QlvJpaiJuKHk50UUkEOVXAmNAuCA7rL78scI68OiC+er6yRTuo78gmpSXp50FQvqdgAoNbnORll69FZTc93zp+7U5xdzxG3H0m5UcUpbWWF7Yrcwj/LLjTVqAf4Cn+4qvWhEKdZIhGHNBp0Zh/W6YAK/wtdGPLghAhoBbaxsb/GgKSErLPWO6C1Xq73dki0k5tEcQDXdYNKvhRUOi+Bnb49RM1Gru+lqFkgCs/K2sCmbPVdQJZOfGGek4qly2FzJ9hzPCzOKai3L9qmZ2u7P9CUE+4pMdI3ov+N6yAx51k3wwjo4LsLoe+x3JPsCZzB8S9NSpscMu2gcvgsy5Ka85mEkwayYhd5DsNGpgTPGBOWdZttP6BCwPK5eLrq9ZuD5TPGPqCsJZDBED5JfPtNqT+UKvJ669eiFy48BmzudHcvUeZV2NC37uGtfGsLOJV4Pab446pwOGwDvfBwA3Ur2w+Ton4ceygiXEKSDm3mGdW7RNbj0aiSQVbCmRJ4UzAA3vA8oq3twVlVRsAWbuJZKotR6QFmBbzV4Mspag7OYPZwXSfN6VkOSEIeoFtq+amuRmJ/d9nYvsk41IOapz7iO0T0Oh1BCrlX85RpUj7QS6LfE+ZmA3CH+62BubINBP7wCzUNZcDHjc+3R2aEQwMwKQyp6bdCZsvAqa2ePaT3QQFuuQgfXUBaLsXJexJ/7PBp21hTum75jezhpo0+r1roXkndKWsCxx1QLFi+Wr8csI9dhIfx9f7S30RvzeocZH4Ukiif0IGSfbJOtbMgl/DrPrDBCil/HgCiYemezoanNAASzEl2i2vHBl3FAR12kBFfoa2cRg6KB4YeVEoSNvs1plNwccRAKynSY3I4TnDToZ0AIeo/+GHioWZLKjQmfYjotVDoWHG2PvklvfE3oxgxxZpD1JkEMi8lQoio4uzL5zx/tN/zCd3fs4qk+JKmW+PftL3WpuLqrrrZkQbnNalAeSFpj7g30gRLfuvPXYnDSBW7WlO5uNmqyIexrT7Xurfx1fWP9IflJlQujM+468mkFHl9BHYwJBaQfuTVfs= X-Microsoft-Antispam-Message-Info: ElE1m3v4U235LaOXJrjrpgrX0xMx2FHEf+i+VNbVcOpzgWE9Bpdd6zln1GgSVFwZwgd6A+J0hzCEvoOHc0Wuy/PlNmrxSY4aJjH+d1+ZfhOrgANs3FvjPbTy64dOKGP5vN+CnR9zDV19QL9S/Q/3CpWr7Y5CLFdfi3CbZV6yfc/i3keEFnXpx59+w2hBjwDnT9H4+OAwpp1TdwZ/8s8RVeW+23YHQnTBl6uhm4PmL1EIjEYTu1GhSSBUsWPABD/FGQPrBvyCMwwPonII0s1H/MhjbZ4Xg+kFMaQFTYyYUaJTn+miq9I17I/V4P0eBc3i/QzDazZeixhAA9Lgu4FcVE+o3VD9955fqRyfNEExu+Y= X-Microsoft-Exchange-Diagnostics: 1; AM5PR0802MB2545; 6:H2ERxffIobZ4hmbYk9jIbzrIZnHmR1SWZRyoX+Rvl+xXca+/B5m1y92Ok8lEV3+VMtTg+XwD2QWXf4GTnMOEFZwPwM/nqzFNxCtlbBYJ2Z9JJX1pOw5X+uu7Vjy9Rlov/rXwcrDqrs/wEgQjV/a6Q+hZSbUlzwKXjxfrH+j2YOo8oy+xDl2b2WeNxLMoaowiXzJpO8ujbhkUxDqE/Lleqmwxu93DUjU1m5AkFmLfuCMBvXA/0ClfWiUSw5K2JggC91n/mvBi58/fv7xqYAZDokkxjxs++SNGxXoJcgIHiYgmnI6P0JpxtcvUnvMyZ737jxGutzebEYKypKJ9KyX1iVatyWV0bM99ajHTHBbuoAUHbSPgZMFEnc4g4mcx0HnwwrSojzODyU4LWyNi/QGiEB67kqSbztsR4LMZE+mLBhiyygYMCbBP35vlJMYQKjxoW68rdjo5vk2M79FW76ZXgg==; 5:ZfPneMm/Zw+evtwM8tO+AZ4xLnp46jbRNTA4t3NLtRJYCWM6iRMThcQg5CWvMvDxKBY5kH12r5vtTlE+qkLhZz0x8Q19yLkJ9+3wCLeFjR3WmT+t2dofQUxbfojSHAX0eFM/li/BjqOaD47T91MtKQGPM94L+Uz4ZvgYspFlMn8=; 7:PTuv1TftBzqRlAO1MWE8O0ZFHC3JtQxDaoqpYAq2jipcMtudnskGRsAtJc3hBu7P0yEP+CQ4r2RtZ6kIoK5prTzVoI2FCZZUNku3nh8kAZUbMXfFuAk4CRxKkgFPBC6A/us1SyTXebtzgq3wb5HoB/SboF9eKBEwquBuc+iDX/CwCw/O7PnN6jpWZP5rYsC6YSuPMhC5/X+d5CbMU32pkPlGEWkiMArh2gYg9j1KXQY+ZCHExs//zdpAiKt1wdRr SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Oct 2018 16:36:31.5532 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c8711db-8725-4aad-4428-08d63060ddfc X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0802MB2545 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd@arm.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Brian Starkey AFBC is a flexible, proprietary, lossless compression protocol and format, with a number of defined DRM format modifiers. To facilitate consistency and compatibility between different AFBC producers and consumers, document the expectations for usage of the AFBC DRM format modifiers in a new .rst chapter. Signed-off-by: Brian Starkey Reviewed-by: Liviu Dudau --- Documentation/gpu/afbc.rst | 233 ++++++++++++++++++++++++++++++++++ Documentation/gpu/drivers.rst | 1 + MAINTAINERS | 1 + include/uapi/drm/drm_fourcc.h | 3 + 4 files changed, 238 insertions(+) create mode 100644 Documentation/gpu/afbc.rst diff --git a/Documentation/gpu/afbc.rst b/Documentation/gpu/afbc.rst new file mode 100644 index 000000000000..922d955da192 --- /dev/null +++ b/Documentation/gpu/afbc.rst @@ -0,0 +1,233 @@ +=================================== + Arm Framebuffer Compression (AFBC) +=================================== + +AFBC is a proprietary lossless image compression protocol and format. +It provides fine-grained random access and minimizes the amount of +data transferred between IP blocks. + +AFBC can be enabled on drivers which support it via use of the AFBC +format modifiers defined in drm_fourcc.h. See DRM_FORMAT_MOD_ARM_AFBC(*). + +All users of the AFBC modifiers must follow the usage guidelines laid +out in this document, to ensure compatibility across different AFBC +producers and consumers. + +Components and Ordering +======================= + +AFBC streams can contain several components - where a component +corresponds to a color channel (i.e. R, G, B, X, A, Y, Cb, Cr). +The assignment of input/output color channels must be consistent +between the encoder and the decoder for correct operation, otherwise +the consumer will interpret the decoded data incorrectly. + +Furthermore, when the lossless colorspace transform is used +(AFBC_FORMAT_MOD_YTR, which should be enabled for RGB buffers for +maximum compression efficiency), the component order must be: + + * Component 0: R + * Component 1: G + * Component 2: B + +The component ordering is communicated via the fourcc code in the +fourcc:modifier pair. In general, component '0' is considered to +reside in the least-significant bits of the corresponding linear +format. For example, COMP(bits): + + * DRM_FORMAT_ABGR8888 + + * Component 0: R(8) + * Component 1: G(8) + * Component 2: B(8) + * Component 3: A(8) + + * DRM_FORMAT_BGR888 + + * Component 0: R(8) + * Component 1: G(8) + * Component 2: B(8) + + * DRM_FORMAT_YUYV + + * Component 0: Y(8) + * Component 1: Cb(8, 2x1 subsampled) + * Component 2: Cr(8, 2x1 subsampled) + +In AFBC, 'X' components are not treated any differently from any other +component. Therefore, an AFBC buffer with fourcc DRM_FORMAT_XBGR8888 +encodes with 4 components, like so: + + * DRM_FORMAT_XBGR8888 + + * Component 0: R(8) + * Component 1: G(8) + * Component 2: B(8) + * Component 3: X(8) + +Please note, however, that the inclusion of a "wasted" 'X' channel is +bad for compression efficiency, and so it's recommended to avoid +formats containing 'X' bits. If a fourth component is +required/expected by the encoder/decoder, then it is recommended to +instead use an equivalent format with alpha, setting all alpha bits to +'1'. If there is no requirement for a fourth component, then a format +which doesn't include alpha can be used, e.g. DRM_FORMAT_BGR888. + +Number of Planes +================ + +Formats which are typically multi-planar in linear layouts (e.g. YUV +420), can be encoded into one, or multiple, AFBC planes. As with +component order, the encoder and decoder must agree about the number +of planes in order to correctly decode the buffer. The fourcc code is +used to determine the number of encoded planes in an AFBC buffer, +matching the number of planes for the linear (unmodified) format. +Within each plane, the component ordering also follows the fourcc +code: + +For example: + + * DRM_FORMAT_YUYV: nplanes = 1 + + * Plane 0: + + * Component 0: Y(8) + * Component 1: Cb(8, 2x1 subsampled) + * Component 2: Cr(8, 2x1 subsampled) + + * DRM_FORMAT_NV12: nplanes = 2 + + * Plane 0: + + * Component 0: Y(8) + + * Plane 1: + + * Component 0: Cb(8, 2x1 subsampled) + * Component 1: Cr(8, 2x1 subsampled) + +Cross-device interoperability +============================= + +For maximum compatibility across devices, the table below defines +canonical formats for use between AFBC-enabled devices. Formats which +are listed here must be used exactly as specified when using the AFBC +modifiers. Formats which are not listed should be avoided. + +.. flat-table:: AFBC formats + + * - Fourcc code + - Description + - Planes/Components + + * - DRM_FORMAT_ABGR2101010 + - 10-bit per component RGB, with 2-bit alpha + - Plane 0: 4 components + * Component 0: R(10) + * Component 1: G(10) + * Component 2: B(10) + * Component 3: A(2) + + * - DRM_FORMAT_ABGR8888 + - 8-bit per component RGB, with 8-bit alpha + - Plane 0: 4 components + * Component 0: R(8) + * Component 1: G(8) + * Component 2: B(8) + * Component 3: A(8) + + * - DRM_FORMAT_BGR888 + - 8-bit per component RGB + - Plane 0: 3 components + * Component 0: R(8) + * Component 1: G(8) + * Component 2: B(8) + + * - DRM_FORMAT_BGR565 + - 5/6-bit per component RGB + - Plane 0: 3 components + * Component 0: R(5) + * Component 1: G(6) + * Component 2: B(5) + + * - DRM_FORMAT_ABGR1555 + - 5-bit per component RGB, with 1-bit alpha + - Plane 0: 4 components + * Component 0: R(5) + * Component 1: G(5) + * Component 2: B(5) + * Component 3: A(1) + + * - DRM_FORMAT_VUY888 + - 8-bit per component YCbCr 444, single plane + - Plane 0: 3 components + * Component 0: Y(8) + * Component 1: Cb(8) + * Component 2: Cr(8) + + * - DRM_FORMAT_VUY101010 + - 10-bit per component YCbCr 444, single plane + - Plane 0: 3 components + * Component 0: Y(10) + * Component 1: Cb(10) + * Component 2: Cr(10) + + * - DRM_FORMAT_YUYV + - 8-bit per component YCbCr 422, single plane + - Plane 0: 3 components + * Component 0: Y(8) + * Component 1: Cb(8, 2x1 subsampled) + * Component 2: Cr(8, 2x1 subsampled) + + * - DRM_FORMAT_NV16 + - 8-bit per component YCbCr 422, two plane + - Plane 0: 1 component + * Component 0: Y(8) + Plane 1: 2 components + * Component 0: Cb(8, 2x1 subsampled) + * Component 1: Cr(8, 2x1 subsampled) + + * - DRM_FORMAT_Y210 + - 10-bit per component YCbCr 422, single plane + - Plane 0: 3 components + * Component 0: Y(10) + * Component 1: Cb(10, 2x1 subsampled) + * Component 2: Cr(10, 2x1 subsampled) + + * - DRM_FORMAT_P210 + - 10-bit per component YCbCr 422, two plane + - Plane 0: 1 component + * Component 0: Y(10) + Plane 1: 2 components + * Component 0: Cb(10, 2x1 subsampled) + * Component 1: Cr(10, 2x1 subsampled) + + * - DRM_FORMAT_YUV420_8BIT + - 8-bit per component YCbCr 420, single plane + - Plane 0: 3 components + * Component 0: Y(8) + * Component 1: Cb(8, 2x2 subsampled) + * Component 2: Cr(8, 2x2 subsampled) + + * - DRM_FORMAT_YUV420_10BIT + - 10-bit per component YCbCr 420, single plane + - Plane 0: 3 components + * Component 0: Y(10) + * Component 1: Cb(10, 2x2 subsampled) + * Component 2: Cr(10, 2x2 subsampled) + + * - DRM_FORMAT_NV12 + - 8-bit per component YCbCr 420, two plane + - Plane 0: 1 component + * Component 0: Y(8) + Plane 1: 2 components + * Component 0: Cb(8, 2x2 subsampled) + * Component 1: Cr(8, 2x2 subsampled) + + * - DRM_FORMAT_P010 + - 10-bit per component YCbCr 420, two plane + - Plane 0: 1 component + * Component 0: Y(10) + Plane 1: 2 components + * Component 0: Cb(10, 2x2 subsampled) + * Component 1: Cr(10, 2x2 subsampled) diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst index 7d2d3875ff1a..8ec755024390 100644 --- a/Documentation/gpu/drivers.rst +++ b/Documentation/gpu/drivers.rst @@ -16,6 +16,7 @@ GPU Driver Documentation vkms bridge/dw-hdmi xen-front + afbc .. only:: subproject and html diff --git a/MAINTAINERS b/MAINTAINERS index 39c3f6682ace..4d3a8822b4c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1091,6 +1091,7 @@ M: Mali DP Maintainers S: Supported F: drivers/gpu/drm/arm/ F: Documentation/devicetree/bindings/display/arm,malidp.txt +F: Documentation/gpu/afbc.rst ARM MFM AND FLOPPY DRIVERS M: Ian Molton diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index f8396d1b8fbd..b2fb2d53fff7 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -586,6 +586,9 @@ extern "C" { * AFBC has several features which may be supported and/or used, which are * represented using bits in the modifier. Not all combinations are valid, * and different devices or use-cases may support different combinations. + * + * Further information on the use of AFBC modifiers can be found in + * Documentation/gpu/afbc.rst */ #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)