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Mon, 29 Oct 2018 17:14:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8EB526E058; Mon, 29 Oct 2018 17:14:43 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from EUR02-VE1-obe.outbound.protection.outlook.com (mail-eopbgr20084.outbound.protection.outlook.com [40.107.2.84]) by gabe.freedesktop.org (Postfix) with ESMTPS id CAE556E052 for ; Mon, 29 Oct 2018 17:14:41 +0000 (UTC) Received: from DB6PR0802MB2551.eurprd08.prod.outlook.com (10.172.251.149) by DB6PR0802MB2248.eurprd08.prod.outlook.com (10.172.227.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1273.19; Mon, 29 Oct 2018 17:14:38 +0000 Received: from DB6PR0802MB2551.eurprd08.prod.outlook.com ([fe80::19ca:93bb:bc0:985a]) by DB6PR0802MB2551.eurprd08.prod.outlook.com ([fe80::19ca:93bb:bc0:985a%7]) with mapi id 15.20.1273.027; Mon, 29 Oct 2018 17:14:38 +0000 From: Alexandru-Cosmin Gheorghe To: "seanpaul@chromium.org" , "airlied@linux.ie" , "dri-devel@lists.freedesktop.org" , Liviu Dudau , Brian Starkey , "malidp@foss.arm.com" , "maxime.ripard@bootlin.com" , "maarten.lankhorst@linux.intel.com" , Ayan Halder , "daniel.vetter@ffwll.ch" , Raymond Smith , David Garbett , Lisa Wu , Matt Szczesiak , Charles Xu , "james qian wang (Arm Technology China)" Subject: [PATCH v6 3/9] drm: mali-dp: Enable Mali-DP tiled buffer formats Thread-Topic: [PATCH v6 3/9] drm: mali-dp: Enable Mali-DP tiled buffer formats Thread-Index: AQHUb6rfYo2IQVDoVEi9Vfv+4Jsx5w== Date: Mon, 29 Oct 2018 17:14:38 +0000 Message-ID: <20181029171419.4512-4-alexandru-cosmin.gheorghe@arm.com> References: <20181029171419.4512-1-alexandru-cosmin.gheorghe@arm.com> In-Reply-To: <20181029171419.4512-1-alexandru-cosmin.gheorghe@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LO2P265CA0032.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:61::20) To DB6PR0802MB2551.eurprd08.prod.outlook.com (2603:10a6:4:a1::21) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [217.140.106.54] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB6PR0802MB2248; H:DB6PR0802MB2551.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: KDxjM6Foc9AdgBaHuih4cspqjULLs4nM/iyiUfj/z7Fi6APrKTIfJH0vUMTxqWkQlKnRtnmlYM7ZVg6AEBOWhn2VK5tdaYiIPKrFbMZHUPMCF0nxZ1RMYCUoUfRZYLU74s3LWTj+LeZWRXRBH8fVDqAYNkolMvxuPSUtFcD9epaZampUXHq2hBLydZ0K8Seqxz7Khv3XkCc+dTeayyyqOtzOFgzJmd5Ya/dt3DleZJCz4Oi/JsTY2gdCzinjGPRmju9WSs8PxHVlJP8/Kfff/cYxmm8pKvkkQr9IxYKPjmvAKzD5uAiEe6tgGlMuFJ44ZHegmIDn594YlG8ibkTEQJ9u9f2WE6Z/Vs/DBXNet/A= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1f083864-0f2a-4cdc-fcc3-08d63dc201d7 X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2018 17:14:38.7569 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0802MB2248 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nd , Alexandru-Cosmin Gheorghe Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Enable the following formats - DRM_FORMAT_X0L0: DP650 - DRM_FORMAT_X0L2: DP550, DP650 Reviewed-by: Brian Starkey Signed-off-by: Alexandru Gheorghe --- drivers/gpu/drm/arm/malidp_hw.c | 14 +++++++++++--- drivers/gpu/drm/arm/malidp_planes.c | 28 +++++++++++++++++++++++++--- 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c index 7aad7dd80d8c..b9bed1138fa3 100644 --- a/drivers/gpu/drm/arm/malidp_hw.c +++ b/drivers/gpu/drm/arm/malidp_hw.c @@ -77,12 +77,18 @@ static const struct malidp_format_id malidp500_de_formats[] = { { DRM_FORMAT_YUYV, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 2) }, \ { DRM_FORMAT_UYVY, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 3) }, \ { DRM_FORMAT_NV12, DE_VIDEO1 | DE_VIDEO2 | SE_MEMWRITE, MALIDP_ID(5, 6) }, \ - { DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) } + { DRM_FORMAT_YUV420, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 7) }, \ + { DRM_FORMAT_X0L2, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(6, 6)} static const struct malidp_format_id malidp550_de_formats[] = { MALIDP_COMMON_FORMATS, }; +static const struct malidp_format_id malidp650_de_formats[] = { + MALIDP_COMMON_FORMATS, + { DRM_FORMAT_X0L0, DE_VIDEO1 | DE_VIDEO2, MALIDP_ID(5, 4)}, +}; + static const struct malidp_layer malidp500_layers[] = { /* id, base address, fb pointer address base, stride offset, * yuv2rgb matrix offset, mmu control register offset, rotation_features @@ -630,6 +636,8 @@ static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, u16 case DRM_FORMAT_BGR565: case DRM_FORMAT_UYVY: case DRM_FORMAT_YUYV: + case DRM_FORMAT_X0L0: + case DRM_FORMAT_X0L2: bytes_per_col = 32; break; /* 16 lines at 1.5 bytes per pixel */ @@ -905,8 +913,8 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = { MALIDP550_DC_IRQ_SE, .vsync_irq = MALIDP550_DC_IRQ_CONF_VALID, }, - .pixel_formats = malidp550_de_formats, - .n_pixel_formats = ARRAY_SIZE(malidp550_de_formats), + .pixel_formats = malidp650_de_formats, + .n_pixel_formats = ARRAY_SIZE(malidp650_de_formats), .bus_align_bytes = 16, }, .query_hw = malidp650_query_hw, diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index 837a24d56675..c9a6d3e0cada 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -398,6 +398,7 @@ static int malidp_de_plane_check(struct drm_plane *plane, struct drm_framebuffer *fb; u16 pixel_alpha = state->pixel_blend_mode; int i, ret; + unsigned int block_w, block_h; if (!state->crtc || !state->fb) return 0; @@ -413,13 +414,26 @@ static int malidp_de_plane_check(struct drm_plane *plane, ms->n_planes = fb->format->num_planes; for (i = 0; i < ms->n_planes; i++) { u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); - if (fb->pitches[i] & (alignment - 1)) { + + if ((fb->pitches[i] * drm_format_info_block_height(fb->format, i)) + & (alignment - 1)) { DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n", fb->pitches[i], i); return -EINVAL; } } + block_w = drm_format_info_block_width(fb->format, 0); + block_h = drm_format_info_block_height(fb->format, 0); + if (fb->width % block_w || fb->height % block_h) { + DRM_DEBUG_KMS("Buffer width/height needs to be a multiple of tile sizes"); + return -EINVAL; + } + if ((state->src_x >> 16) % block_w || (state->src_y >> 16) % block_h) { + DRM_DEBUG_KMS("Plane src_x/src_y needs to be a multiple of tile sizes"); + return -EINVAL; + } + if ((state->crtc_w > mp->hwdev->max_line_size) || (state->crtc_h > mp->hwdev->max_line_size) || (state->crtc_w < mp->hwdev->min_line_size) || @@ -492,10 +506,18 @@ static void malidp_de_set_plane_pitches(struct malidp_plane *mp, num_strides = (mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) ? 3 : 2; - for (i = 0; i < num_strides; ++i) - malidp_hw_write(mp->hwdev, pitches[i], + /* + * The drm convention for pitch is that it needs to cover width * cpp, + * but our hardware wants the pitch/stride to cover all rows included + * in a tile. + */ + for (i = 0; i < num_strides; ++i) { + unsigned int block_h = drm_format_info_block_height(mp->base.state->fb->format, i); + + malidp_hw_write(mp->hwdev, pitches[i] * block_h, mp->layer->base + mp->layer->stride_offset + i * 4); + } } static const s16