From patchwork Fri Nov 2 21:31:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 10666183 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4772417DB for ; Fri, 2 Nov 2018 21:29:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 39DBD2B34E for ; Fri, 2 Nov 2018 21:29:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2DF662B485; Fri, 2 Nov 2018 21:29:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E76902B34E for ; Fri, 2 Nov 2018 21:29:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C6296E602; Fri, 2 Nov 2018 21:28:57 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C9A86E5D3; Fri, 2 Nov 2018 21:28:53 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Nov 2018 14:28:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,457,1534834800"; d="scan'208";a="93304566" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.151]) by FMSMGA003.fm.intel.com with ESMTP; 02 Nov 2018 14:28:52 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v8 15/19] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Date: Fri, 2 Nov 2018 14:31:34 -0700 Message-Id: <20181102213138.301-16-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181102213138.301-1-manasi.d.navare@intel.com> References: <20181102213138.301-1-manasi.d.navare@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Manasi Navare , Anusha Srivatsa MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP DSC PPS secondary data packet infoframes are filled with DSC picure parameter set metadata according to the DSC standard. These infoframes are sent to the sink device and used during DSC decoding. v3: * Rename to intel_dp_write_pps_sdp (Ville) * Use const intel_crtc_state (Ville) v2: * Rebase ond drm-tip Cc: Jani Nikula Cc: Ville Syrjala Cc: Anusha Srivatsa Signed-off-by: Manasi Navare Reviewed-by: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 0eaa69778160..85af5f784aad 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -988,6 +988,25 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, } } +static void intel_dp_write_dsc_pps_sdp(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dp_dsc_cfg; + struct drm_dsc_pps_infoframe dp_dsc_pps_sdp; + + /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */ + drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp); + + /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */ + drm_dsc_pps_infoframe_pack(&dp_dsc_pps_sdp, vdsc_cfg); + + intel_dig_port->write_infoframe(encoder, crtc_state, + DP_SDP_PPS, &dp_dsc_pps_sdp, + sizeof(dp_dsc_pps_sdp)); +} + void intel_dsc_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -997,5 +1016,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, intel_configure_pps_for_dsc_encoder(encoder, crtc_state); + intel_dp_write_dsc_pps_sdp(encoder, crtc_state); + return; }