| Message ID | 20181113232149.22753-4-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | CRTC background color | expand |
On Tue, Nov 13, 2018 at 03:21:49PM -0800, Matt Roper wrote: > Gen9+ platforms allow CRTC's to be programmed with a background/canvas > color below the programmable planes. Let's expose this for use by > compositors. > > v2: > - Split out bgcolor sanitization and programming of csc/gamma bits to a > separate patch that we can land before the ABI changes are ready to > go in. (Ville) > - Change a temporary variable name to be more consistent with > other similar functions. (Ville) > - Change register name to SKL_CANVAS for consistency with the > CHV_CANVAS register. > > Cc: dri-devel@lists.freedesktop.org > Cc: wei.c.li@intel.com > Cc: harish.krupo.kps@intel.com > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++++++ > drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++++++++++++++++++------- > 2 files changed, 37 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 670db5073d70..1f2a19e6ec79 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -3254,6 +3254,15 @@ static int i915_display_info(struct seq_file *m, void *unused) > intel_plane_info(m, crtc); > } > > + if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) { > + uint64_t background = pipe_config->base.bgcolor; > + > + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n", > + DRM_RGBA_RED(background, 10), > + DRM_RGBA_GREEN(background, 10), > + DRM_RGBA_BLUE(background, 10)); > + } > + > seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", > yesno(!crtc->cpu_fifo_underrun_disabled), > yesno(!crtc->pch_fifo_underrun_disabled)); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 1d089d93d88b..e7a759e0c021 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3834,6 +3834,27 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) > clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); > } > > +static void skl_update_background_color(const struct intel_crtc_state *cstate) s/cstate/crtc_state/ please > +{ > + struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + uint64_t propval = cstate->base.bgcolor; > + uint32_t tmp; > + > + /* Hardware is programmed with 10 bits of precision */ > + tmp = DRM_RGBA_RED(propval, 10) << 20 > + | DRM_RGBA_GREEN(propval, 10) << 10 > + | DRM_RGBA_BLUE(propval, 10); > + > + /* > + * Set CSC and gamma for bottom color to ensure background pixels > + * receive the same color transformations as plane content. > + */ > + tmp |= SKL_CANVAS_CSC_ENABLE | SKL_CANVAS_GAMMA_ENABLE; > + > + I915_WRITE_FW(SKL_CANVAS(crtc->pipe), tmp); Why _FW?
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 670db5073d70..1f2a19e6ec79 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3254,6 +3254,15 @@ static int i915_display_info(struct seq_file *m, void *unused) intel_plane_info(m, crtc); } + if (INTEL_GEN(dev_priv) >= 9 && pipe_config->base.active) { + uint64_t background = pipe_config->base.bgcolor; + + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n", + DRM_RGBA_RED(background, 10), + DRM_RGBA_GREEN(background, 10), + DRM_RGBA_BLUE(background, 10)); + } + seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", yesno(!crtc->cpu_fifo_underrun_disabled), yesno(!crtc->pch_fifo_underrun_disabled)); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1d089d93d88b..e7a759e0c021 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3834,6 +3834,27 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) clear_bit(I915_RESET_MODESET, &dev_priv->gpu_error.flags); } +static void skl_update_background_color(const struct intel_crtc_state *cstate) +{ + struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + uint64_t propval = cstate->base.bgcolor; + uint32_t tmp; + + /* Hardware is programmed with 10 bits of precision */ + tmp = DRM_RGBA_RED(propval, 10) << 20 + | DRM_RGBA_GREEN(propval, 10) << 10 + | DRM_RGBA_BLUE(propval, 10); + + /* + * Set CSC and gamma for bottom color to ensure background pixels + * receive the same color transformations as plane content. + */ + tmp |= SKL_CANVAS_CSC_ENABLE | SKL_CANVAS_GAMMA_ENABLE; + + I915_WRITE_FW(SKL_CANVAS(crtc->pipe), tmp); +} + static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -3869,14 +3890,8 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta ironlake_pfit_disable(old_crtc_state); } - /* - * We don't (yet) allow userspace to control the pipe background color, - * so force it to black, but apply pipe gamma and CSC so that its - * handling will match how we program our planes. - */ if (INTEL_GEN(dev_priv) >= 9) - I915_WRITE(SKL_CANVAS(crtc->pipe), - SKL_CANVAS_GAMMA_ENABLE | SKL_CANVAS_CSC_ENABLE); + skl_update_background_color(new_crtc_state); } static void intel_fdi_normal_train(struct intel_crtc *crtc) @@ -10896,6 +10911,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, crtc_state->planes_changed = true; } + if (crtc_state->bgcolor_changed) + pipe_config->update_pipe = true; + ret = 0; if (dev_priv->display.compute_pipe_wm) { ret = dev_priv->display.compute_pipe_wm(pipe_config); @@ -14035,6 +14053,9 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); + if (INTEL_GEN(dev_priv) >= 9) + drm_crtc_add_bgcolor_property(&intel_crtc->base); + return 0; fail:
Gen9+ platforms allow CRTC's to be programmed with a background/canvas color below the programmable planes. Let's expose this for use by compositors. v2: - Split out bgcolor sanitization and programming of csc/gamma bits to a separate patch that we can land before the ABI changes are ready to go in. (Ville) - Change a temporary variable name to be more consistent with other similar functions. (Ville) - Change register name to SKL_CANVAS for consistency with the CHV_CANVAS register. Cc: dri-devel@lists.freedesktop.org Cc: wei.c.li@intel.com Cc: harish.krupo.kps@intel.com Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 9 +++++++++ drivers/gpu/drm/i915/intel_display.c | 35 ++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 7 deletions(-)