From patchwork Wed Nov 14 01:52:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 10681863 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A331018F0 for ; Wed, 14 Nov 2018 01:51:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 96EF42B34A for ; Wed, 14 Nov 2018 01:51:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 889472B347; Wed, 14 Nov 2018 01:51:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3CF302B347 for ; Wed, 14 Nov 2018 01:51:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 969D16E43D; Wed, 14 Nov 2018 01:50:33 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CAAA6E438; Wed, 14 Nov 2018 01:50:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Nov 2018 17:50:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,230,1539673200"; d="scan'208";a="279622669" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.151]) by fmsmga005.fm.intel.com with ESMTP; 13 Nov 2018 17:50:13 -0800 From: Manasi Navare To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v9 19/24] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Date: Tue, 13 Nov 2018 17:52:27 -0800 Message-Id: <20181114015232.21952-20-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181114015232.21952-1-manasi.d.navare@intel.com> References: <20181114015232.21952-1-manasi.d.navare@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Manasi Navare , Rodrigo Vivi Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP A separate power well 2 (PG2) is required for VDSC on eDP transcoder whereas all other transcoders use the power wells associated with the transcoders for VDSC. This patch adds a helper to obtain correct power domain depending on transcoder being used and enables/disables the power wells during VDSC enabling/disabling. v4: * Get VDSC power domain only if compression en is set in crtc_state (Ville, Imre) v3: * Call it intel_dsc_power_domain, add to intel_ddi_get_power_domains (Ville) v2: * Fix tabs, const crtc_state, fix comments (Ville) Suggested-by: Ville Syrjala Cc: Ville Syrjala Cc: Imre Deak Cc: Rodrigo Vivi Signed-off-by: Manasi Navare Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_ddi.c | 6 ++++++ drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_vdsc.c | 25 +++++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index f6279e54f15b..0638fd2febfb 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2154,6 +2154,12 @@ static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder, intel_port_is_tc(dev_priv, encoder->port)) domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port)); + /* + * VDSC power is needed when DSC is enabled + */ + if (crtc_state->dsc_params.compression_enable) + domains |= BIT_ULL(intel_dsc_power_domain(crtc_state)); + return domains; } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 5b53fc262b91..92e987fc3d9f 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1857,6 +1857,8 @@ uint8_t intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, /* intel_vdsc.c */ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config); +enum intel_display_power_domain +intel_dsc_power_domain(const struct intel_crtc_state *crtc_state); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index c0b0c8211481..58366cbc6045 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -578,6 +578,24 @@ int intel_dp_compute_dsc_params(struct intel_dp *intel_dp, return intel_compute_rc_parameters(vdsc_cfg); } +enum intel_display_power_domain +intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) +{ + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + /* + * On ICL VDSC/joining for eDP transcoder uses a separate power well PW2 + * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain. + * For any other transcoder, VDSC/joining uses the power well associated + * with the pipe/transcoder in use. Hence another reference on the + * transcoder power domain will suffice. + */ + if (cpu_transcoder == TRANSCODER_EDP) + return POWER_DOMAIN_TRANSCODER_EDP_VDSC; + else + return POWER_DOMAIN_TRANSCODER(cpu_transcoder); +} + static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -1017,6 +1035,10 @@ void intel_dsc_enable(struct intel_encoder *encoder, if (!crtc_state->dsc_params.compression_enable) return; + /* Enable Power wells for VDSC/joining */ + intel_display_power_get(dev_priv, + intel_dsc_power_domain(crtc_state)); + intel_configure_pps_for_dsc_encoder(encoder, crtc_state); intel_dp_write_dsc_pps_sdp(encoder, crtc_state); @@ -1069,4 +1091,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) RIGHT_BRANCH_VDSC_ENABLE); I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + /* Disable Power wells for VDSC/joining */ + intel_display_power_put(dev_priv, + intel_dsc_power_domain(old_crtc_state)); }