| Message ID | 20181120183736.28054-23-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Respin of remaining DSC + FEC patches | expand |
On Tue, Nov 20, 2018 at 10:37:35AM -0800, Manasi Navare wrote: > From: Anusha Srivatsa <anusha.srivatsa@intel.com> > > If FEC is supported, the corresponding > DP_TP_CTL register bits have to be configured. > > The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register > and wait till FEC_STATUS in DP_TP_CTL[28] is 1. > Also add the warn message to make sure that the control > register is already active while enabling FEC. > > v2: > - Change commit message. Configure fec state after > link training (Manasi, Gaurav) > - Remove redundent checks (Manasi) > - Remove the registers that get added automagically (Anusha) > > v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav) > > v4: rebased. > > v5: > - Move the code to the proper spot, according to spec.(Ville) > - Use fec state as a check too. > > v6: Pass intel_encoder, instead of intel_dp. (Ville) > > v7: Remove unwanted comments (Manasi) > > Cc: dri-devel@lists.freedesktop.org > Cc: Gaurav K Singh <gaurav.k.singh@intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com> > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > drivers/gpu/drm/i915/intel_ddi.c | 23 +++++++++++++++++++++++ > 2 files changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 21e82c03cf80..5713754ace99 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9198,6 +9198,7 @@ enum skl_power_gate { > #define _DP_TP_CTL_B 0x64140 > #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) > #define DP_TP_CTL_ENABLE (1 << 31) > +#define DP_TP_CTL_FEC_ENABLE (1 << 30) > #define DP_TP_CTL_MODE_SST (0 << 27) > #define DP_TP_CTL_MODE_MST (1 << 27) > #define DP_TP_CTL_FORCE_ACT (1 << 25) > @@ -9216,6 +9217,7 @@ enum skl_power_gate { > #define _DP_TP_STATUS_A 0x64044 > #define _DP_TP_STATUS_B 0x64144 > #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) > +#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) > #define DP_TP_STATUS_IDLE_DONE (1 << 25) > #define DP_TP_STATUS_ACT_SENT (1 << 24) > #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index b778e6fed5f8..78d8dcaa1618 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -3112,6 +3112,27 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, > DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); > } > > +static void intel_ddi_enable_fec(struct intel_encoder *encoder, > + const struct intel_crtc_state *crtc_state) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + enum port port = encoder->port; > + u32 val; > + > + if (!crtc_state->fec_enable) > + return; > + > + val = I915_READ(DP_TP_CTL(port)); > + val |= DP_TP_CTL_FEC_ENABLE; > + I915_WRITE(DP_TP_CTL(port), val); > + > + if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port), > + DP_TP_STATUS_FEC_ENABLE_LIVE, > + DP_TP_STATUS_FEC_ENABLE_LIVE, > + 1)) > + DRM_ERROR("Timed out waiting for FEC Enable Status\n"); > +} > + > static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state, > const struct drm_connector_state *conn_state) > @@ -3157,6 +3178,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) > intel_dp_stop_link_train(intel_dp); > > + intel_ddi_enable_fec(encoder, crtc_state); > + > icl_enable_phy_clock_gating(dig_port); > > if (!is_mst) > -- > 2.19.1 >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 21e82c03cf80..5713754ace99 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9198,6 +9198,7 @@ enum skl_power_gate { #define _DP_TP_CTL_B 0x64140 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) #define DP_TP_CTL_ENABLE (1 << 31) +#define DP_TP_CTL_FEC_ENABLE (1 << 30) #define DP_TP_CTL_MODE_SST (0 << 27) #define DP_TP_CTL_MODE_MST (1 << 27) #define DP_TP_CTL_FORCE_ACT (1 << 25) @@ -9216,6 +9217,7 @@ enum skl_power_gate { #define _DP_TP_STATUS_A 0x64044 #define _DP_TP_STATUS_B 0x64144 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) +#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) #define DP_TP_STATUS_IDLE_DONE (1 << 25) #define DP_TP_STATUS_ACT_SENT (1 << 24) #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b778e6fed5f8..78d8dcaa1618 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -3112,6 +3112,27 @@ static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, DRM_DEBUG_KMS("Failed to set FEC_READY in the sink\n"); } +static void intel_ddi_enable_fec(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum port port = encoder->port; + u32 val; + + if (!crtc_state->fec_enable) + return; + + val = I915_READ(DP_TP_CTL(port)); + val |= DP_TP_CTL_FEC_ENABLE; + I915_WRITE(DP_TP_CTL(port), val); + + if (intel_wait_for_register(dev_priv, DP_TP_STATUS(port), + DP_TP_STATUS_FEC_ENABLE_LIVE, + DP_TP_STATUS_FEC_ENABLE_LIVE, + 1)) + DRM_ERROR("Timed out waiting for FEC Enable Status\n"); +} + static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) @@ -3157,6 +3178,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) intel_dp_stop_link_train(intel_dp); + intel_ddi_enable_fec(encoder, crtc_state); + icl_enable_phy_clock_gating(dig_port); if (!is_mst)