From patchwork Tue Nov 27 00:37:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10699551 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A658114D6 for ; Tue, 27 Nov 2018 00:37:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9674A28438 for ; Tue, 27 Nov 2018 00:37:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8ADDB2A509; Tue, 27 Nov 2018 00:37:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 42CF728438 for ; Tue, 27 Nov 2018 00:37:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2F73B89CAF; Tue, 27 Nov 2018 00:37:36 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 862F789C1A; Tue, 27 Nov 2018 00:37:15 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Nov 2018 16:37:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,284,1539673200"; d="scan'208";a="113078558" Received: from josouza-mobl.jf.intel.com ([10.24.11.14]) by fmsmga001.fm.intel.com with ESMTP; 26 Nov 2018 16:37:14 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Subject: [PATCH 8/9] drm/i915/psr: Set the right frames values Date: Mon, 26 Nov 2018 16:37:09 -0800 Message-Id: <20181127003710.18618-8-jose.souza@intel.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181127003710.18618-1-jose.souza@intel.com> References: <20181127003710.18618-1-jose.souza@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= , Dhinakaran Pandiyan , dri-devel@lists.freedesktop.org, Rodrigo Vivi Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP() was being set with the number of frames that it should wait to enter PSR, what is wrong. Here it is setting this field with the highest value to avoid PSR2 exits frequently, as when HW exit deep sleep it needs to go to idle state causing a PSR exit for then waiting a few frames before activate PSR2 again. This will result in more power saving as the sleep state also provide some power savings by doing selective updates instead of full screen updates. About EDP_PSR2_FRAMES_BEFORE_ACTIVATE() it is the number of frames (not idle frames) that PSR2 hardware will wait to activate PSR2, so lets keep using the sink sync latency. Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index ba7bbe3f8df2..6fd793fec5e9 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -482,13 +482,13 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) struct i915_psr *psr = &dev_priv->psr; u32 val; - /* Let's use 6 as the minimum to cover all known cases including the - * off-by-one issue that HW has in some cases. + /* sink_sync_latency of 8 means source has to wait for more than 8 + * frames, we'll go with 9 frames for now */ - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); + val = EDP_PSR2_FRAMES_BEFORE_ACTIVATE(psr->sink_sync_latency + 1); - idle_frames = max(idle_frames, psr->sink_sync_latency + 1); - val = EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP(idle_frames); + /* Avoid deep sleep as much as possible to avoid PSR2 idle state */ + val |= EDP_PSR2_IDLE_FRAMES_TO_DEEP_SLEEP(15); /* FIXME: selective update is probably totally broken because it doesn't * mesh at all with our frontbuffer tracking. And the hw alone isn't @@ -497,8 +497,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) val |= EDP_Y_COORDINATE_ENABLE; - val |= EDP_PSR2_FRAMES_BEFORE_ACTIVATE(psr->sink_sync_latency + 1); - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) val |= EDP_PSR2_TP2_TIME_50us;