From patchwork Fri Nov 30 02:25:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10705683 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 11AA114E2 for ; Fri, 30 Nov 2018 02:25:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 033492FC80 for ; Fri, 30 Nov 2018 02:25:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EB94A2FC92; Fri, 30 Nov 2018 02:25:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A17562FC80 for ; Fri, 30 Nov 2018 02:25:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 181CD6E58B; Fri, 30 Nov 2018 02:25:36 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 22B9E6E571; Fri, 30 Nov 2018 02:25:33 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Nov 2018 18:25:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,297,1539673200"; d="scan'208";a="94323521" Received: from josouza-mobl.jf.intel.com ([10.24.11.14]) by orsmga007.jf.intel.com with ESMTP; 29 Nov 2018 18:25:31 -0800 From: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= To: intel-gfx@lists.freedesktop.org Subject: [PATCH v2 11/11] drm/i915/psr: Set the right frames values Date: Thu, 29 Nov 2018 18:25:25 -0800 Message-Id: <20181130022525.25676-11-jose.souza@intel.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181130022525.25676-1-jose.souza@intel.com> References: <20181130022525.25676-1-jose.souza@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= , Dhinakaran Pandiyan , dri-devel@lists.freedesktop.org, Rodrigo Vivi Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP EDP_PSR2_FRAME_BEFORE_SU() is the number of frames that PSR2 HW will wait before enter in PSR2 activation state, important to note here is that it will wait for X frames not X idle frames. So lets reuse the previous approch to get the maximum number of frames between 6 and sink_sync_latency to enter in PSR2 activation state and just remove the VBT idle_frames. And EDP_PSR2_FRAME_BEFORE_SU() is the number of idle frames that PSR2 HW will wait before enter in PSR2 deep sleep when PSR2 is active. Important note here is that HW will need to go to PSR2 idle state every time it exits PSR2 deep sleep, so avoid as much as possible deep sleep will provide in overal more power savings as PSR2 sleep will save some power as memory will not be read in the idle frames and screen will be partialy updated without exit PSR2. Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 0257dbcf9384..36c2eb27ed8d 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -489,18 +489,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) /* Let's use 6 as the minimum to cover all known cases including the * off-by-one issue that HW has in some cases. + * sink_sync_latency of 8 means source has to wait for more than 8 + * frames, so sink_sync_latency + 1. */ - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); + val = max(6, dev_priv->psr.sink_sync_latency + 1); + val = min_t(u32, val, EDP_PSR2_FRAME_BEFORE_SU_MAX); + val = EDP_PSR2_FRAME_BEFORE_SU(val); - idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); - val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; + /* Avoid deep sleep as much as possible to avoid PSR2 idle state */ + val |= EDP_PSR2_IDLE_FRAME(EDP_PSR2_IDLE_FRAME_MAX); val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) val |= EDP_Y_COORDINATE_ENABLE; - val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); - if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 && dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50) val |= EDP_PSR2_TP2_TIME_50us;