| Message ID | 20181201005759.28093-3-eric@anholt.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/6] drm/v3d: Document cache flushing ABI. | expand |
On Sat, 1 Dec 2018 at 00:58, Eric Anholt <eric@anholt.net> wrote: > > This is the write combiner for TMU writes. You're supposed to flush > that at job end if you had dirtied any cachelines. Flushing it at job > start then doesn't make any sense. > > Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Dave Emett <david.emett@broadcom.com> > Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+") > --- > drivers/gpu/drm/v3d/v3d_gem.c | 12 ------------ > 1 file changed, 12 deletions(-) > > diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c > index 34103205b7cb..cc4d025b01e0 100644 > --- a/drivers/gpu/drm/v3d/v3d_gem.c > +++ b/drivers/gpu/drm/v3d/v3d_gem.c > @@ -139,22 +139,10 @@ v3d_invalidate_l2(struct v3d_dev *v3d, int core) > V3D_L2CACTL_L2CENA); > } > > -static void > -v3d_invalidate_l1td(struct v3d_dev *v3d, int core) > -{ > - V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); > - if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & > - V3D_L2TCACTL_L2TFLS), 100)) { > - DRM_ERROR("Timeout waiting for L1T write combiner flush\n"); > - } > -} > - > /* Invalidates texture L2 cachelines */ > static void > v3d_flush_l2t(struct v3d_dev *v3d, int core) > { > - v3d_invalidate_l1td(v3d, core); > - > V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, > V3D_L2TCACTL_L2TFLS | > V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM)); > -- > 2.20.0.rc1 >
diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c index 34103205b7cb..cc4d025b01e0 100644 --- a/drivers/gpu/drm/v3d/v3d_gem.c +++ b/drivers/gpu/drm/v3d/v3d_gem.c @@ -139,22 +139,10 @@ v3d_invalidate_l2(struct v3d_dev *v3d, int core) V3D_L2CACTL_L2CENA); } -static void -v3d_invalidate_l1td(struct v3d_dev *v3d, int core) -{ - V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); - if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & - V3D_L2TCACTL_L2TFLS), 100)) { - DRM_ERROR("Timeout waiting for L1T write combiner flush\n"); - } -} - /* Invalidates texture L2 cachelines */ static void v3d_flush_l2t(struct v3d_dev *v3d, int core) { - v3d_invalidate_l1td(v3d, core); - V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_L2TFLS | V3D_SET_FIELD(V3D_L2TCACTL_FLM_FLUSH, V3D_L2TCACTL_FLM));
This is the write combiner for TMU writes. You're supposed to flush that at job end if you had dirtied any cachelines. Flushing it at job start then doesn't make any sense. Signed-off-by: Eric Anholt <eric@anholt.net> Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+") --- drivers/gpu/drm/v3d/v3d_gem.c | 12 ------------ 1 file changed, 12 deletions(-)