| Message ID | 20190125032314.20915-2-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: sun8i: a23: Enable display pipeline | expand |
On Fri, Jan 25, 2019 at 8:54 AM Chen-Yu Tsai <wens@csie.org> wrote: > > The PLL-MIPI clock is somewhat special as it has its own LDOs which > need to be turned on for this PLL to actually work and output a clock > signal. > > Add the 2 LDO enable bits to the gate bits. > > Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU") > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c > index a4fa2945f230..4b5f8f4e4ab8 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c > @@ -144,7 +144,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", > 8, 4, /* N */ > 4, 2, /* K */ > 0, 4, /* M */ > - BIT(31), /* gate */ > + BIT(31) | BIT(23) | BIT(22), /* gate */ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c index a4fa2945f230..4b5f8f4e4ab8 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c @@ -144,7 +144,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", 8, 4, /* N */ 4, 2, /* K */ 0, 4, /* M */ - BIT(31), /* gate */ + BIT(31) | BIT(23) | BIT(22), /* gate */ BIT(28), /* lock */ CLK_SET_RATE_UNGATE);
The PLL-MIPI clock is somewhat special as it has its own LDOs which need to be turned on for this PLL to actually work and output a clock signal. Add the 2 LDO enable bits to the gate bits. Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU") Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi-ng/ccu-sun8i-a23.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)