From patchwork Mon Mar 18 17:19:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Kleiner X-Patchwork-Id: 10858247 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4BDB717EF for ; Mon, 18 Mar 2019 17:20:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2665D2939F for ; Mon, 18 Mar 2019 17:20:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A1C929065; Mon, 18 Mar 2019 17:20:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD05928066 for ; Mon, 18 Mar 2019 17:20:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7EBE897E0; Mon, 18 Mar 2019 17:20:29 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB7B6897E7; Mon, 18 Mar 2019 17:20:27 +0000 (UTC) Received: by mail-wm1-x343.google.com with SMTP id t124so13645214wma.4; Mon, 18 Mar 2019 10:20:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GlX8dmNdsMj4BRk1A8r8WPXIkP0KMHtBn3L0X3o7PhM=; b=s2TXXa3/hUpm7MSGrS6thMwfWSrQa1jxDPpHaALH3nVjog3mlGKmwnYFz3dWlYsK7L 15MI/LaOndhlUTA1PtLXDSslxHqKJs7kwFPNwfT9zf6zyxkHKtSPJayVXO8JkMRk9uMo Si9T+i/0MIGM8MOYPrrtS2d9kMyQYt2Q+dCXSyCQet3tzJuQcxbzH+WfDSiseS+gHXNU JNRrBVzrQNXtCx96p9s0EegYy8fTPUd3bR1yzKwCwGGD9j0XVxgZ8SUbgonHnVrmxY8Z JbbyI57vrAyMrWIcebRhWtZe1SZA4bZmJtJfUxs98tldjxWGBvlk65MC3wIwtSL4vyQx 9AFw== X-Gm-Message-State: APjAAAXcHM5CYOoVrXQ89PFPVX5AMaA1GygOf3dtki4EzfFCqToPJbyV 16N2rbOZ8OdMlRnFu1ZjjGlgHHUU X-Google-Smtp-Source: APXvYqy/Pn5sfedjMQL7n4wE1cblMIc0yYpOfKi2f+puOPWVajle3mICzdTOr+6kpHbvASE9s2zpLA== X-Received: by 2002:a1c:f510:: with SMTP id t16mr11625438wmh.105.1552929626239; Mon, 18 Mar 2019 10:20:26 -0700 (PDT) Received: from twisty.cin.medizin.uni-tuebingen.de ([2a01:c22:d43c:e500:e9fd:d3f1:412c:598a]) by smtp.gmail.com with ESMTPSA id d9sm21415814wrn.72.2019.03.18.10.20.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Mar 2019 10:20:25 -0700 (PDT) From: Mario Kleiner To: amd-gfx@lists.freedesktop.org Subject: [PATCH 2/4] drm/amd/display: Rework vrr flip throttling for late vblank irq. Date: Mon, 18 Mar 2019 18:19:50 +0100 Message-Id: <20190318171952.24302-3-mario.kleiner.de@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190318171952.24302-1-mario.kleiner.de@gmail.com> References: <20190318171952.24302-1-mario.kleiner.de@gmail.com> X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GlX8dmNdsMj4BRk1A8r8WPXIkP0KMHtBn3L0X3o7PhM=; b=nGVbPBGVc9m5qhWOkrcWQSjpPUk9EuVDUMRsW4FZQ12AwC73tcEWIFXvIiwvW++x4k Og76V4M8b/9TM0D/SFroP4xlOMcZHvhtU30fAMKlvBGbvihA5N5TQ6cjuvbGJddsRID6 eZyUNK7d/ZOJhQDPNePYBLb5AwIx2wylGLsL5O/24wZBCHzYSC3Hgz6kN6lPcv5bLTGg fDorRX9zP32b86WpkmTTnDMSr/jJ7kXY3aZ+9hBb14OPsCQY/4nZ2jSuE7P2nrmuIWCm cT7oP1yAgMoH4cVOnig/ihWOY0tsO5z2XUZwuoKUvnr0w9IvGCgWJ4rIHfWjPa+Irq4B AQ2g== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nicholas.kazlauskas@amd.com, dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP For throttling to work correctly, we always need a baseline vblank count last_flip_vblank that increments at start of front-porch. This is the case for drm_crtc_vblank_count() in non-VRR mode, where the vblank irq fires at start of front-porch and triggers DRM core vblank handling, but it is no longer the case in VRR mode, where core vblank handling is done later, after end of front-porch. Therefore drm_crtc_vblank_count() is no longer useful for this. We also can't use drm_crtc_accurate_vblank_count(), as that would screw up vblank timestamps in VRR mode when called in front-porch. To solve this, use the cooked hardware vblank counter returned by amdgpu_get_vblank_counter_kms() instead, as that one is cooked to always increment at start of front-porch, independent of when vblank related irq's fire. This patch allows vblank irq handling to happen anywhere within vblank of even after it, without a negative impact on flip throttling, so followup patches can shift the vblank core handling trigger point wherever they need it. Signed-off-by: Mario Kleiner Reviewed-by: Nicholas Kazlauskas --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++---------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 889e443..add238f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -406,7 +406,7 @@ struct amdgpu_crtc { struct amdgpu_flip_work *pflip_works; enum amdgpu_flip_status pflip_status; int deferred_flip_completion; - u64 last_flip_vblank; + u32 last_flip_vblank; /* pll sharing */ struct amdgpu_atom_ss ss; bool ss_enabled; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c1c3815..85e4f87 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -286,7 +286,7 @@ static void dm_pflip_high_irq(void *interrupt_params) } /* Update to correct count(s) if racing with vblank irq */ - amdgpu_crtc->last_flip_vblank = drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); + drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); /* wake up userspace */ if (amdgpu_crtc->event) { @@ -298,6 +298,14 @@ static void dm_pflip_high_irq(void *interrupt_params) } else WARN_ON(1); + /* Keep track of vblank of this flip for flip throttling. We use the + * cooked hw counter, as that one incremented at start of this vblank + * of pageflip completion, so last_flip_vblank is the forbidden count + * for queueing new pageflips if vsync + VRR is enabled. + */ + amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev, + amdgpu_crtc->crtc_id); + amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; spin_unlock_irqrestore(&adev->ddev->event_lock, flags); @@ -4769,9 +4777,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, unsigned long flags; struct amdgpu_bo *abo; uint64_t tiling_flags; - uint32_t target, target_vblank; - uint64_t last_flip_vblank; - bool vrr_active = acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE; + uint32_t target_vblank, last_flip_vblank; + bool vrr_active = amdgpu_dm_vrr_active(acrtc_state); bool pflip_present = false; struct { @@ -4918,7 +4925,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * clients using the GLX_OML_sync_control extension or * DRI3/Present extension with defined target_msc. */ - last_flip_vblank = drm_crtc_vblank_count(pcrtc); + last_flip_vblank = amdgpu_get_vblank_counter_kms(dm->ddev, acrtc_attach->crtc_id); } else { /* For variable refresh rate mode only: @@ -4934,11 +4941,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); } - target = (uint32_t)last_flip_vblank + wait_for_vblank; - - /* Prepare wait for target vblank early - before the fence-waits */ - target_vblank = target - (uint32_t)drm_crtc_vblank_count(pcrtc) + - amdgpu_get_vblank_counter_kms(pcrtc->dev, acrtc_attach->crtc_id); + target_vblank = last_flip_vblank + wait_for_vblank; /* * Wait until we're out of the vertical blank period before the one