| Message ID | 20190401171724.215780-8-dianders@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/panel: simple: Add mode support to devicetree | expand |
Am Montag, 1. April 2019, 19:17:24 CEST schrieb Douglas Anderson: > Just like we did for rk3288-veyron-chromebook, we want to be able to > use one of the fixed PLLs in the system to make the pixel clock for > minnie. > > Specifying these timings matches us with how the display is used on > the downstream Chrome OS kernel. See https://crrev.com/c/323211. > > Unlike what we did for rk3288-veyron-chromebook, this CL actually > changes the timings (though not the pixel clock) that is used when > using the upstream kernel. Booting up a minnie shows that it ended up > with a 66.67 MHz pixel clock but it was still using the > porches/blankings it would have wanted for a 72.5 MHz pixel clock. > > NOTE: compared to the downstream kernel, this seems to cause a > slightly different result reported in the 'modetest' command on a > Chromebook. The downstream kernel shows: > 1280x800 60 1280 1298 1330 1351 800 804 822 830 66667 > > With this patch we have: > 1280x800 59 1280 1298 1330 1351 800 804 822 830 66666 > > Specifically modetest was reporting 60 Hz on the downstream kernel but > the upstream kernel does the math and comesup with 59 (because we > actually achieve 59.45 Hz). Also upstream doesn't round the Hz up > when converting to kHz--it seems to truncate. > > ALSO NOTE: when I look at the EDID from the datasheet, I see: > -hsync -vsync > ...but it seems like we've never actually run with that so I've > continued leaving that out. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> applied for 5.4 Thanks Heiko
diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index ca7512ade222..8179cf9f6e98 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -144,6 +144,18 @@ power-supply= <&panel_regulator>; /delete-node/ panel-timing; + + panel-timing { + clock-frequency = <66666667>; + hactive = <1280>; + hfront-porch = <18>; + hback-porch = <21>; + hsync-len = <32>; + vactive = <800>; + vfront-porch = <4>; + vback-porch = <8>; + vsync-len = <18>; + }; }; &rk808 {
Just like we did for rk3288-veyron-chromebook, we want to be able to use one of the fixed PLLs in the system to make the pixel clock for minnie. Specifying these timings matches us with how the display is used on the downstream Chrome OS kernel. See https://crrev.com/c/323211. Unlike what we did for rk3288-veyron-chromebook, this CL actually changes the timings (though not the pixel clock) that is used when using the upstream kernel. Booting up a minnie shows that it ended up with a 66.67 MHz pixel clock but it was still using the porches/blankings it would have wanted for a 72.5 MHz pixel clock. NOTE: compared to the downstream kernel, this seems to cause a slightly different result reported in the 'modetest' command on a Chromebook. The downstream kernel shows: 1280x800 60 1280 1298 1330 1351 800 804 822 830 66667 With this patch we have: 1280x800 59 1280 1298 1330 1351 800 804 822 830 66666 Specifically modetest was reporting 60 Hz on the downstream kernel but the upstream kernel does the math and comesup with 59 (because we actually achieve 59.45 Hz). Also upstream doesn't round the Hz up when converting to kHz--it seems to truncate. ALSO NOTE: when I look at the EDID from the datasheet, I see: -hsync -vsync ...but it seems like we've never actually run with that so I've continued leaving that out. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- Changes in v5: - It's not just jerry, it's most rk3288 Chromebooks (Heiko) Changes in v4: - rk3288-veyron-minnie patch new for v4. Changes in v3: None Changes in v2: None arch/arm/boot/dts/rk3288-veyron-minnie.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)