From patchwork Tue Apr 2 21:52:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 10882383 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 08B251708 for ; Tue, 2 Apr 2019 21:50:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E93B6287FF for ; Tue, 2 Apr 2019 21:50:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E7A942899B; Tue, 2 Apr 2019 21:50:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A1B99287FF for ; Tue, 2 Apr 2019 21:50:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 59BFA6E3CD; Tue, 2 Apr 2019 21:50:41 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id DFB0E6E35B; Tue, 2 Apr 2019 21:50:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Apr 2019 14:50:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,302,1549958400"; d="scan'208";a="137052586" Received: from labuser-z97x-ud5h.jf.intel.com ([10.54.75.151]) by fmsmga008.fm.intel.com with ESMTP; 02 Apr 2019 14:50:38 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] drm/i915/edp: Use max link rate and lane count if eDP EDID quirk Date: Tue, 2 Apr 2019 14:52:35 -0700 Message-Id: <20190402215235.29895-2-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190402215235.29895-1-manasi.d.navare@intel.com> References: <20190402215235.29895-1-manasi.d.navare@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Manasi Navare Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Some eDP 1.4 panels cannot use the optimized fast and narrow pipe config approach, but they need to use th maximum supported lane count for the link training to succeed. There is a DRM EDID quirk for such panels that gets set after reading their corresponding EDID. So if it is set, this patch forces the max lane count in compute_config() hook to use max lane count for link training. Cc: Clint Taylor Cc: Ville Syrjälä Tested-by: Albert Astals Cid Tested-by: Emanuele Panigati Tested-by: Ralgor Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959 Signed-off-by: Manasi Navare Reviewed-by: Clint Taylor --- drivers/gpu/drm/i915/intel_dp.c | 5 ++++- drivers/gpu/drm/i915/intel_drv.h | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 72c49070ed14..421db00f5792 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2028,7 +2028,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, limits.min_bpp = 6 * 3; limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); - if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) { + if (intel_dp->edp_force_max_lane_count || (intel_dp_is_edp(intel_dp) && + intel_dp->edp_dpcd[0] < DP_EDP_14)) { /* * Use the maximum clock and number of lanes the eDP panel * advertizes being capable of. The eDP 1.3 and earlier panels @@ -7101,6 +7102,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, edid = drm_get_edid(connector, &intel_dp->aux.ddc); if (edid) { if (drm_add_edid_modes(connector, edid)) { + if (connector->display_info.force_max_lane_count) + intel_dp->edp_force_max_lane_count = true; drm_connector_update_edid_property(connector, edid); } else { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f8c7b291fdc3..c67c3c518714 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1327,6 +1327,9 @@ struct intel_dp { /* Display stream compression testing */ bool force_dsc_en; + + /* eDP 1.4 EDID quirk to use max lane count */ + bool edp_force_max_lane_count; }; enum lspcon_vendor {