From patchwork Tue Jun 18 19:05:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 11002545 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 837616C5 for ; Tue, 18 Jun 2019 19:05:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74959288E8 for ; Tue, 18 Jun 2019 19:05:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5F26D28B50; Tue, 18 Jun 2019 19:05:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1D35728AF1 for ; Tue, 18 Jun 2019 19:05:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 484EA6E21F; Tue, 18 Jun 2019 19:05:56 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id AC1D16E22C for ; Tue, 18 Jun 2019 19:05:54 +0000 (UTC) Received: from localhost.localdomain (unknown [194.230.155.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 80B6320863; Tue, 18 Jun 2019 19:05:49 +0000 (UTC) From: Krzysztof Kozlowski To: David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , Kukjin Kim , Catalin Marinas , Will Deacon , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Marek Szyprowski , Olof Johansson , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Subject: [RFT 02/10] clk: samsung: Add bus clock for GPU/G3D on Exynos4412 Date: Tue, 18 Jun 2019 21:05:26 +0200 Message-Id: <20190618190534.4951-3-krzk@kernel.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190618190534.4951-1-krzk@kernel.org> References: <20190618190534.4951-1-krzk@kernel.org> X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1560884754; bh=jXXvRsijbHdSjSp46+Gnvv9t0hiH6dZfxuMdrgfPP4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kdKwCHQUekeguYgskUHWlqZI387UPs/rDnQ++hEuIb/RZ0SAIcp1KCiVR1w1pA3Df gExJXnw7TirweJC2pIbed4utGYBVQRdlTWk8cNaqnvu7mDOpPqpWaJ7FG8te0lY5Fk oAbz/68kBa/rXtsrkw+qx4RwNxAbnbF8PikOriDc= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joseph Kogut , Krzysztof Kozlowski , Arnd Bergmann , Bartlomiej Zolnierkiewicz MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos4.c | 1 + include/dt-bindings/clock/exynos4.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index d2a68a792a21..ed4af7da9c4f 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -961,6 +961,7 @@ static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { /* list of gate clocks supported in exynos4x12 soc */ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { + GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0), GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index a0439ce8e8d3..88ec3968b90a 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -187,6 +187,7 @@ #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 +#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */