@@ -244,7 +244,10 @@ static bool always_valid(struct drm_i915_private *i915)
static bool needs_fence_registers(struct drm_i915_private *i915)
{
- return !intel_gt_is_wedged(&i915->gt);
+ if (intel_gt_is_wedged(&i915->gt))
+ return false;
+
+ return i915->ggtt.num_fences;
}
static bool needs_mi_store_dword(struct drm_i915_private *i915)
@@ -184,6 +184,9 @@ static int igt_partial_tiling(void *arg)
int tiling;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
/* We want to check the page mapping and fencing of a large object
* mmapped through the GTT. The object we create is larger than can
* possibly be mmaped as a whole, and so we must use partial GGTT vma.
@@ -1179,8 +1179,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
struct i915_request *rq;
struct evict_vma arg;
struct hang h;
+ unsigned int pin_flags;
int err;
+ if (!gt->ggtt->num_fences && flags & EXEC_OBJECT_NEEDS_FENCE)
+ return 0;
+
if (!engine || !intel_engine_can_store_dword(engine))
return 0;
@@ -1217,10 +1221,12 @@ static int __igt_reset_evict_vma(struct intel_gt *gt,
goto out_obj;
}
- err = i915_vma_pin(arg.vma, 0, 0,
- i915_vma_is_ggtt(arg.vma) ?
- PIN_GLOBAL | PIN_MAPPABLE :
- PIN_USER);
+ pin_flags = i915_vma_is_ggtt(arg.vma) ? PIN_GLOBAL : PIN_USER;
+
+ if (flags & EXEC_OBJECT_NEEDS_FENCE)
+ pin_flags |= PIN_MAPPABLE;
+
+ err = i915_vma_pin(arg.vma, 0, 0, pin_flags);
if (err) {
i915_request_add(rq);
goto out_obj;
@@ -42,6 +42,9 @@ static void trash_stolen(struct drm_i915_private *i915)
unsigned long page;
u32 prng = 0x12345678;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return;
+
for (page = 0; page < size; page += PAGE_SIZE) {
const dma_addr_t dma = i915->dsm.start + page;
u32 __iomem *s;
@@ -1147,6 +1147,9 @@ static int igt_ggtt_page(void *arg)
unsigned int *order, n;
int err;
+ if (!HAS_MAPPABLE_APERTURE(i915))
+ return 0;
+
mutex_lock(&i915->drm.struct_mutex);
obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
We may be missing support for the mappable aperture on some platforms. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> --- .../drm/i915/gem/selftests/i915_gem_coherency.c | 5 ++++- drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 3 +++ drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 14 ++++++++++---- drivers/gpu/drm/i915/selftests/i915_gem.c | 3 +++ drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +++ 5 files changed, 23 insertions(+), 5 deletions(-)