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Tue, 10 Sep 2019 01:00:16 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM05-CO1-obe.outbound.protection.outlook.com (mail-eopbgr720040.outbound.protection.outlook.com [40.107.72.40]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE1E78931F; Tue, 10 Sep 2019 01:00:14 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GM81j6mlUwUGGR5wXTaa9uKWRrxWvUuQQy+sHj3jNvlTqrVgVuLjBgq6RF2bIngq2rvNVxIaHD17Hg3ueyKdwoCXU08CX+dgpKQfl0IJP6mAYKLnw2m1xMNLgCMQpfHShyoX1xqcf6OmeuE66tq7UR+C4YDlPDZSJDhK+zN6W9Idg5KiKbRsNwl/K35JIDioZoSb2tkT9qjxVklFRr51LEjzwnKx+IiuTT5Dzs2Db3/7NCQnY8pM0EVkZA4S8U2MqAn//7kQ4f7IsTMuZERwNZgiChSzXrYejNsesqTiGzO1tGIKN8789SvB0UAvh8/aSboTw1OgQo/osLBZp3E4xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GhRezt7syK6D9DXh8N4JXpN1i9ZVQeyPCyWLlmmSNFU=; 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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GhRezt7syK6D9DXh8N4JXpN1i9ZVQeyPCyWLlmmSNFU=; b=PaYh/v/7/lpfTIErw5As4+9sKLDwoesUCDfxFPhZcFzX/TkQmrmYEKFfY8wMS+wrfYIItrAMuzetViq/hHTtld0YI7UCkIhu93MS3EkIGsTRRGb/5McARbtBXxMd1MFPqF/FABt2uGlVffq9buJAUysSjdrhajYJfPTlmNi2zyI= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Rodrigo.Siqueira@amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Li, Sun peng \(Leo\)" , "Berthe, Abdoulaye" , Manasi Navare Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This change adds definitions required for Link Training-tunable PHY Repeater, which was introduced in the DP 1.3 specification, and incremented with new features in the DP 1.4*. Changes since V4: - Update commit message - Fix misleading comments related to the spec version Changes since V3: - Replace spaces by tabs Changes since V2: - Drop the kernel-doc comment - Reorder LTTPR according to register offset Changes since V1: - Adjusts registers names to be aligned with spec and the rest of the file - Update spec comment from 1.4 to 1.4a Cc: Abdoulaye Berthe Cc: Harry Wentland Cc: Leo Li Cc: Jani Nikula Cc: Manasi Navare Cc: Ville Syrjälä Signed-off-by: Rodrigo Siqueira Signed-off-by: Abdoulaye Berthe Reviewed-by: Harry Wentland --- include/drm/drm_dp_helper.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 7972b925a952..b1a9a0dcc177 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -966,6 +966,31 @@ #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 +/* Link Training (LT)-tunable PHY Repeaters */ +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ +#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ +#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ + /* DP HDCP message start offsets in DPCD address space */ #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET