From patchwork Fri Sep 20 09:04:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 11154111 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B1366912 for ; Fri, 20 Sep 2019 09:05:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 994AB207E0 for ; Fri, 20 Sep 2019 09:05:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 994AB207E0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D50C56FBE9; Fri, 20 Sep 2019 09:05:34 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailgw01.mediatek.com (unknown [1.203.163.78]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C97D6FBE9 for ; Fri, 20 Sep 2019 09:05:30 +0000 (UTC) X-UUID: 7cde274937f34fdca87ecd7b42519fc7-20190920 X-UUID: 7cde274937f34fdca87ecd7b42519fc7-20190920 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1603609500; Fri, 20 Sep 2019 17:05:24 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 20 Sep 2019 17:05:24 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 20 Sep 2019 17:05:23 +0800 From: Jitao Shi To: CK Hu , David Airlie , Daniel Vetter , Subject: [PATCH v7 5/5] drm/mediatek: config mipitx impedance with calibration data Date: Fri, 20 Sep 2019 17:04:32 +0800 Message-ID: <20190920090432.3308-6-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190920090432.3308-1-jitao.shi@mediatek.com> References: <20190920090432.3308-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E1555B9150FE0CBC966DF8EC2076947C1CCB6C5CC9A6E569B07C02DCBC234FE42000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jitao Shi , srv_heupstream@mediatek.com, stonea168@163.com, cawa.cheng@mediatek.com, sj.huang@mediatek.com, linux-mediatek@lists.infradead.org, Matthias Brugger , yingjoe.chen@mediatek.com, eddie.huang@mediatek.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Config mipitx impedance with calibration data to make sure their impedance are 100ohm. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 1 + drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 63 +++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h index eea44327fe9f..a1b6292145de 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h @@ -28,6 +28,7 @@ struct mtk_mipi_tx { void __iomem *regs; u32 data_rate; u32 mipitx_drive; + u32 rt_code[5]; const struct mtk_mipitx_data *driver_data; struct clk_hw pll_hw; struct clk *pll; diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c index 5bda8355145f..9ca90dee095a 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c @@ -5,6 +5,8 @@ */ #include "mtk_mipi_tx.h" +#include +#include #define MIPITX_LANE_CON 0x000c #define RG_DSI_CPHY_T1DRV_EN BIT(0) @@ -28,6 +30,7 @@ #define MIPITX_PLL_CON4 0x003c #define RG_DSI_PLL_IBIAS (3 << 10) +#define MIPITX_D2P_RTCODE 0x0100 #define MIPITX_D2_SW_CTL_EN 0x0144 #define MIPITX_D0_SW_CTL_EN 0x0244 #define MIPITX_CK_CKMODE_EN 0x0328 @@ -108,6 +111,64 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { .recalc_rate = mtk_mipi_tx_pll_recalc_rate, }; +static int mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) +{ + u32 *buf = NULL; + int i, j; + struct nvmem_cell *cell; + struct device *dev = mipi_tx->dev; + size_t len; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + dev_warn(dev, "nvmem_cell_get fail\n"); + return -EINVAL; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) { + dev_warn(dev, "can't get data\n"); + return -EINVAL; + } + + if (len < 3 * sizeof(u32)) { + dev_warn(dev, "invalid calibration data\n"); + kfree(buf); + return -EINVAL; + } + + mipi_tx->rt_code[0] = ((buf[0] >> 6 & 0x1F) << 5) | + (buf[0] >> 11 & 0x1F); + mipi_tx->rt_code[1] = ((buf[1] >> 27 & 0x1F) << 5) | + (buf[0] >> 1 & 0x1F); + mipi_tx->rt_code[2] = ((buf[1] >> 17 & 0x1F) << 5) | + (buf[1] >> 22 & 0x1F); + mipi_tx->rt_code[3] = ((buf[1] >> 7 & 0x1F) << 5) | + (buf[1] >> 12 & 0x1F); + mipi_tx->rt_code[4] = ((buf[2] >> 27 & 0x1F) << 5) | + (buf[1] >> 2 & 0x1F); + + for (i = 0; i < 5; i++) { + if ((mipi_tx->rt_code[i] & 0x1F) == 0) + mipi_tx->rt_code[i] |= 0x10; + + if ((mipi_tx->rt_code[i] >> 5 & 0x1F) == 0) + mipi_tx->rt_code[i] |= 0x10 << 5; + + for (j = 0; j < 10; j++) { + mtk_mipi_tx_update_bits(mipi_tx, + MIPITX_D2P_RTCODE * (i + 1) + j * 4, + 1, mipi_tx->rt_code[i] >> j & 1); + } + } + + kfree(buf); + return 0; +} + static void mtk_mipi_tx_power_on_signal(struct phy *phy) { struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); @@ -130,6 +191,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) RG_DSI_HSTX_LDO_REF_SEL, mipi_tx->mipitx_drive << 6); + mtk_mipi_tx_config_calibration_data(mipi_tx); + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); }