| Message ID | 20190926105256.61412-4-kholk11@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DRM/MSM: Add support for MSM8956 and Adreno 510 | expand |
On Thu, Sep 26, 2019 at 12:52:54PM +0200, kholk11@gmail.com wrote: > From: "Angelo G. Del Regno" <kholk11@gmail.com> > > The 28nm PLL has a different iospace on MSM/APQ family B SoCs: > add a new configuration and use it when the DT reports the > "qcom,dsi-phy-28nm-hpm-fam-b" compatible. > > Signed-off-by: Angelo G. Del Regno <kholk11@gmail.com> > --- > .../devicetree/bindings/display/msm/dsi.txt | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 18 ++++++++++++++++++ > 4 files changed, 22 insertions(+) > > diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt > index af95586c898f..d3ba9ee22f38 100644 > --- a/Documentation/devicetree/bindings/display/msm/dsi.txt > +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt > @@ -83,6 +83,7 @@ DSI PHY: > Required properties: > - compatible: Could be the following > * "qcom,dsi-phy-28nm-hpm" > + * "qcom,dsi-phy-28nm-hpm-fam-b" > * "qcom,dsi-phy-28nm-lp" > * "qcom,dsi-phy-20nm" > * "qcom,dsi-phy-28nm-8960" Same comment here re: putting binding updates in separate patches. Sean > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index 4097eca1b3ef..507c0146a305 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -481,6 +481,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY > { .compatible = "qcom,dsi-phy-28nm-hpm", > .data = &dsi_phy_28nm_hpm_cfgs }, > + { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b", > + .data = &dsi_phy_28nm_hpm_famb_cfgs }, > { .compatible = "qcom,dsi-phy-28nm-lp", > .data = &dsi_phy_28nm_lp_cfgs }, > #endif > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index c4069ce6afe6..24b294ed3059 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -40,6 +40,7 @@ struct msm_dsi_phy_cfg { > }; > > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > index b3f678f6c2aa..3b9300545e16 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c > @@ -142,6 +142,24 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { > .num_dsi_phy = 2, > }; > > +const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { > + .type = MSM_DSI_PHY_28NM_HPM, > + .src_pll_truthtable = { {true, true}, {false, true} }, > + .reg_cfg = { > + .num = 1, > + .regs = { > + {"vddio", 100000, 100}, > + }, > + }, > + .ops = { > + .enable = dsi_28nm_phy_enable, > + .disable = dsi_28nm_phy_disable, > + .init = msm_dsi_phy_init_common, > + }, > + .io_start = { 0x1a94400, 0x1a94800 }, > + .num_dsi_phy = 2, > +}; > + > const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { > .type = MSM_DSI_PHY_28NM_LP, > .src_pll_truthtable = { {true, true}, {true, true} }, > -- > 2.21.0 >
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index af95586c898f..d3ba9ee22f38 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -83,6 +83,7 @@ DSI PHY: Required properties: - compatible: Could be the following * "qcom,dsi-phy-28nm-hpm" + * "qcom,dsi-phy-28nm-hpm-fam-b" * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 4097eca1b3ef..507c0146a305 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -481,6 +481,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { #ifdef CONFIG_DRM_MSM_DSI_28NM_PHY { .compatible = "qcom,dsi-phy-28nm-hpm", .data = &dsi_phy_28nm_hpm_cfgs }, + { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b", + .data = &dsi_phy_28nm_hpm_famb_cfgs }, { .compatible = "qcom,dsi-phy-28nm-lp", .data = &dsi_phy_28nm_lp_cfgs }, #endif diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index c4069ce6afe6..24b294ed3059 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -40,6 +40,7 @@ struct msm_dsi_phy_cfg { }; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index b3f678f6c2aa..3b9300545e16 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -142,6 +142,24 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = { .num_dsi_phy = 2, }; +const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs = { + .type = MSM_DSI_PHY_28NM_HPM, + .src_pll_truthtable = { {true, true}, {false, true} }, + .reg_cfg = { + .num = 1, + .regs = { + {"vddio", 100000, 100}, + }, + }, + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + .init = msm_dsi_phy_init_common, + }, + .io_start = { 0x1a94400, 0x1a94800 }, + .num_dsi_phy = 2, +}; + const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .type = MSM_DSI_PHY_28NM_LP, .src_pll_truthtable = { {true, true}, {true, true} },