From patchwork Tue Oct 1 16:17:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lipski, Mikita" X-Patchwork-Id: 11169231 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 43E6617EE for ; Tue, 1 Oct 2019 16:18:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2C0FA20679 for ; Tue, 1 Oct 2019 16:18:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2C0FA20679 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C96776E862; Tue, 1 Oct 2019 16:17:56 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-eopbgr770055.outbound.protection.outlook.com [40.107.77.55]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D4896E85F; Tue, 1 Oct 2019 16:17:53 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AC2EpuHKmrgl9HGET1LnEtL1tlUPJj1TV1nWbGLBuE6b4W5uyi7sxLqWFGrOnvbzNBwmKSiXAcxMC7m/5NkaFzV4UpyZtVWVt4JvMx67iK3CvblpU61+NT3E2d5LR5lFu6GBg/Rf1HnO/GKn+GbfdpqZvAAOFD6kvLL+ARd8u9f5IC47cGy7kXjdx8mhshwGrXha1ulYxzb1GZ4VA5xW6XfIHriF935XDQf+OcowcAdINrO0PMjgrDEOjjFWWpovyadg4SDE+8dmMV7AYmh2TV8F78i2mWPhxj+zC65FnRZWGKthHQ37Jqm48eJf/f4x4y1zuTjJp9F6zOAI4LCL1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sggqry2rHdBKGLVlluhu/5dBl0eopBo0TyVURrldDDI=; b=OnXPPjnuHk2ZXUpuq5o+lx9OkhCJvVsbljwYPBaGY9NiBjYgqhZqeWS6T2u42R1jLnh7Hla5FL7NSJDOtkEW0twgCUKm6I2VqSyACk7E6XipjA6ii4G2g9zju/xGrhahDhc4WXw2uRdcmHbnrkhgpzZPrzaPEujcKMmLwJJDXTHNLw0S/y/bHy5MwolTb1cDQ+ZB3vAhf5UJUV5Fg71cQc6kWrfP6S7QLgKckNUMeodm+OXLLYo6GWWeUcO4dah1+eKSp2I91NAVGD8QXD52vC8KL+7m2TlEjqdcAOV1TpZf9e7MsdldvyMqCr1Cg3k/EgkZT9f8FOd3hy7oGX/vdg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 165.204.84.17) smtp.rcpttodomain=redhat.com smtp.mailfrom=amd.com; dmarc=permerror action=none header.from=amd.com; dkim=none (message not signed); arc=none Received: from BN8PR12CA0016.namprd12.prod.outlook.com (2603:10b6:408:60::29) by DM6PR12MB3196.namprd12.prod.outlook.com (2603:10b6:5:184::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2305.20; Tue, 1 Oct 2019 16:17:50 +0000 Received: from CO1NAM03FT027.eop-NAM03.prod.protection.outlook.com (2a01:111:f400:7e48::205) by BN8PR12CA0016.outlook.office365.com (2603:10b6:408:60::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2241.18 via Frontend Transport; Tue, 1 Oct 2019 16:17:49 +0000 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXCHOV02.amd.com (165.204.84.17) by CO1NAM03FT027.mail.protection.outlook.com (10.152.80.161) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2305.15 via Frontend Transport; Tue, 1 Oct 2019 16:17:48 +0000 Received: from mlipski-pc.amd.com (10.180.168.240) by SATLEXCHOV02.amd.com (10.181.40.72) with Microsoft SMTP Server id 14.3.389.1; Tue, 1 Oct 2019 11:17:41 -0500 From: To: Subject: [PATCH 14/14] drm/amd/display: Trigger modesets on MST DSC connectors Date: Tue, 1 Oct 2019 12:17:21 -0400 Message-ID: <20191001161721.13793-15-mikita.lipski@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191001161721.13793-14-mikita.lipski@amd.com> References: <20191001161721.13793-1-mikita.lipski@amd.com> <20191001161721.13793-2-mikita.lipski@amd.com> <20191001161721.13793-3-mikita.lipski@amd.com> <20191001161721.13793-4-mikita.lipski@amd.com> <20191001161721.13793-5-mikita.lipski@amd.com> <20191001161721.13793-6-mikita.lipski@amd.com> <20191001161721.13793-7-mikita.lipski@amd.com> <20191001161721.13793-8-mikita.lipski@amd.com> <20191001161721.13793-9-mikita.lipski@amd.com> <20191001161721.13793-10-mikita.lipski@amd.com> <20191001161721.13793-11-mikita.lipski@amd.com> <20191001161721.13793-12-mikita.lipski@amd.com> <20191001161721.13793-13-mikita.lipski@amd.com> <20191001161721.13793-14-mikita.lipski@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(396003)(136003)(346002)(376002)(39860400002)(428003)(199004)(189003)(76176011)(70586007)(7696005)(486006)(5660300002)(476003)(26005)(11346002)(50466002)(446003)(6666004)(126002)(356004)(305945005)(51416003)(70206006)(1076003)(478600001)(2616005)(36756003)(47776003)(336012)(16586007)(86362001)(8936002)(8676002)(2906002)(81166006)(81156014)(4326008)(53416004)(186003)(48376002)(426003)(2351001)(50226002)(54906003)(316002)(2876002)(6916009)(14444005)(5024004)(16060500001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM6PR12MB3196; H:SATLEXCHOV02.amd.com; FPR:; SPF:None; LANG:en; PTR:InfoDomainNonexistent; A:1; MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9e3a807f-4be2-4e2b-32f3-08d7468ae6f6 X-MS-TrafficTypeDiagnostic: DM6PR12MB3196: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-Forefront-PRVS: 0177904E6B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DVB8tJpU2YoI2x1AbWKfKAuDy8NkfgA1ZPEScMctLAKOaKBQjBHJeLGZDyU//FhYi77ewAB4hi9YVuY3CcLvkiDgeYP1Vk0TtDj4C0Mula2wQeMmHB80rnkEx6hj+QnGkn3FT5IhwrfJiD/2QocKBSYtX6GbrjXfY1zBSJ6Fhp0JL3g4PQtpd57CYmX//Ug50ibwgFdUal3DpYISUrYWejNMfEsKhUNNYxFYDgwmaR9Y4FRseLhhLQuf6S4zYBXQVa2K58C82LkOVbm+HGMmOlir/4kU/MfNzC8NlCCx8Yi7QLHVEx5caI2QsjvwYrtKM0jpegDY9g67GVNfQkEhB0jEky70saB+jCbuHoD++omKgRY4JnUDXevj0RthXVX2f5yN1jcNOMd5myFE0zmhswHzbr6sXN5RsKLMxYRovfY= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2019 16:17:48.8428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e3a807f-4be2-4e2b-32f3-08d7468ae6f6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXCHOV02.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3196 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sggqry2rHdBKGLVlluhu/5dBl0eopBo0TyVURrldDDI=; b=1v3gfv4wfKCMhF90KrX/C6K1ZfEE5Kb/DpHdi0oorbpIXjrJ4UN5XHxyPJnk2PB3yYYm67Xay5Zka3rQbLgtMkKP2Y2LhUck9wtOe/O3RSG7sgfomenJ88keUKxzwKzLzzk4bIUV7tIgoKO/U4nRE/CP0TmTvjRmEq6+sVNAbwk= X-Mailman-Original-Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; redhat.com; dkim=none (message not signed) header.d=none;redhat.com; dmarc=permerror action=none header.from=amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leo Li , David Francis , Nicholas Kazlauskas , dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: David Francis Whenever a connector on an MST network is attached, detached, or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if that stream did not change timing. Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset, for each crtc that shares a MST topology with that stream and supports DSC, add that crtc (and all affected connectors and planes) to the atomic state and set mode_changed on its state v2: Do this check only on Navi and before adding connectors and planes on modesetting crtcs Cc: Leo Li Cc: Nicholas Kazlauskas Cc: Lyude Paul Signed-off-by: David Francis --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7501ce2233ed..371086a67c68 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6888,6 +6888,74 @@ static int do_aquire_global_lock(struct drm_device *dev, return ret < 0 ? ret : 0; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +/* + * TODO: This logic should at some point be moved into DRM + */ +static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) +{ + struct drm_connector *connector; + struct drm_connector_state *conn_state; + struct drm_connector_list_iter conn_iter; + struct drm_crtc_state *new_crtc_state; + struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add; + int i, j; + struct drm_crtc *crtcs_affected[AMDGPU_MAX_CRTCS] = { 0 }; + + for_each_new_connector_in_state(state, connector, conn_state, i) { + if (conn_state->crtc != crtc) + continue; + + aconnector = to_amdgpu_dm_connector(connector); + if (!aconnector->port) + aconnector = NULL; + else + break; + } + + if (!aconnector) + return 0; + + i = 0; + drm_connector_list_iter_begin(state->dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + if (!connector->state || !connector->state->crtc) + continue; + + aconnector_to_add = to_amdgpu_dm_connector(connector); + if (!aconnector_to_add->port) + continue; + + if (aconnector_to_add->port->mgr != aconnector->port->mgr) + continue; + + if (!aconnector_to_add->dc_sink) + continue; + + if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported) + continue; + + if (i >= AMDGPU_MAX_CRTCS) + continue; + + crtcs_affected[i] = connector->state->crtc; + i++; + } + drm_connector_list_iter_end(&conn_iter); + + for (j = 0; j < i; j++) { + new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + new_crtc_state->mode_changed = true; + } + + return 0; + +} +#endif + static void get_freesync_config_for_crtc( struct dm_crtc_state *new_crtc_state, struct dm_connector_state *new_con_state) @@ -7577,6 +7645,17 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (adev->asic_type >= CHIP_NAVI10) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { + ret = add_affected_mst_dsc_crtcs(state, crtc); + if (ret) + goto fail; + } + } + } +#endif for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->color_mgmt_changed &&