[PULL] drm-intel-next

Hi Dave & Daniel, Back from XDC, so here comes the first bunch of features. For uAPI: immutable zpos plane property added, disallow userptr import of GGTT mmapped buffer and disallow tiling Other than that loads of early Tigerlake enabling and many Icelake fixups. DP MST and PSR fixes as well as audio tweaks. Gen7 and Cherryview are back to aliasing ppGTT from full, for being too fragile with the timing of the flush calls. And yeah, we eliminated struct_mutex as BKL, now only used for execbuffer and working towards dma_resv replacing it. (perf and GVT corner cases are to be cleaned up). So that is an end to 2 year journey. Regards, Joonas *** drm-intel-next-2019-10-07: UAPI Changes: - Never allow userptr into the mappable GGTT (Chris) No existing users. Avoid anyone from even trying to spare a deadlock scenario. Cross-subsystem Changes: Core Changes: Driver Changes: - Eliminate struct_mutex use as BKL! (Chris) Only used for execbuf serialisation. - Initialize DDI TC and TBT ports (D-I) on Tigerlake (Lucas) - Fix DKL link training for 2.7GHz and 1.62GHz (Jose) - Add Tigerlake DKL PHY programming sequences (Clinton) - Add Tigerlake Thunderbolt PLL divider values (Imre) - drm/i915: Use helpers for drm_mm_node booleans (Chris) - Restrict L3 remapping sysfs interface to dwords (Chris) - Fix audio power up sequence for gen10+ display (Kai) - Skip redundant execlist resubmission (Chris) - Only unwedge if we can reset GPU first (Chris) - Initialise breadcrumb lists on the virtual engine (Chris) - Don't rely on kernel context existing during early errors (Matt A) - Update Icelake+ MG_DP_MODE programming table (Clinton) - Update DMC firmware for Icelake (Anusha) - Downgrade DP MST error after unplugging TypeC cable (Srinivasan) - Limit MST modes based on plane size too (Ville) - Polish intel_tv_mode_valid() (Ville) - Fix g4x sprite scaling stride check with GTT remapping (Ville) - Don't advertize non-exisiting crtcs (Ville) - Clean up encoder->crtc_mask setup (Ville) - Use tc_port instead of port parameter to MG registers (Jose) - Remove static variable for aux last status (Jani) - Implement a better i945gm vblank irq vs. C-states workaround (Ville) - Make the object creation interface consistent (CQ) - Rename intel_vga_msr_write() to intel_vga_reset_io_mem() (Jani, Ville) - Eliminate previous drm_dbg/drm_err usage (Jani) - Move gmbus setup down to intel_modeset_init() (Jani) - Abstract all vgaarb access to intel_vga.[ch] (Jani) - Split out i915_switcheroo.[ch] from i915_drv.c (Jani) - Use intel_gt in has_reset* (Chris) - Eliminate return value for i915_gem_init_early (Matt A) - Selftest improvements (Chris) - Update HuC firmware header version number format (Daniele) drm-intel-next-2019-09-27: UAPI Changes: - Revert "drm/i915: Fix DP-MST crtc_mask" to avoid MST regressions (Ville) - Disable set/get_tiling ioctl on Gen12+ as hardware is gone (Daniel) - Add immutable zpos plane properties (Ville) - Report dual-subslice count as subslices for Tigerlake (Daniele) Driver Changes: <TIGERLAKE ENABLING> - Enable HDCP 1.4 and 2.2 on Gen12+ (Ramalingam) - Enable display state buffer (DSB) batch-programming (Animesh) - Add 12 BPC support for Tigerlake (Anusha) - Add maximum resolution supported by PSR2 HW for Tigerlake (Jose) - Only allow PSR2 on supporting transcoders (Jose) - Disable pipes in reverse order to comply with MST for Tigerlake+ (Jose) - Implement Tigerlake DisplayPort training sequence (Jose) - Do not apply WaIncreaseDefaultTLBEntries from Gen12 onwards (Michel) - Reuse Icelake OA context logic for Tigerlake (Michel) - Enable VD HCP/MFX sub-pipe power gating (Michel) - Use separate context for relocations to deal with Tigerlake pre-parser (Daniele) - Enabling DSC on Pipe A for Tigerlake (Madhumitha) - Remove Yf tiling and legacy CCS support starting Tigerlake (Dhinakaran) - Remove PSR link standby support starting Tigerlake (Jose) - Access the right register when handling PSR interruptions (Jose) - Move DP_TP_* registers from port to transcoder for Tigerlake (Lucas) - Disable SAGV for Tigerlake (Lucas) - Reuse Gen11 stolen initialization for Gen12 (Lucas) - Apply FBC WA for Tigerlake too (Jose) - Use engine relative LRIs on context setup for Tigerlake (Mika, Daniele) - Register state context definition for Gen12 (Michel) - Extend MI_SEMAPHORE_WAIT instruction for Tigerlake (Chris) - Disable various Tigerlake features in attempt to have stable CI results (Chris) - Add Tigerlake W/A to disable CPS aware color pipe by setting chicken bit (Radhakrishna) - Add Tigerlake W/A to Enable Small PL for power benefit (Michel) - Add missing DDI clock select during DP init sequence for Tigerlake (Clinton) - Add missing update_active_dpll callback on Tigerlake (Clinton) - Finish modular FIA support on registers for Tigerlake (Jose) - Unify disable and enable phy clock gating functions on Tigerlake (Jose) - Check the UC health of TC controllers after power on (Jose) - Add TigerLake bandwidth checking (Stanislav) - Add Pipe D cursor ctrl register for Gen12 (Ankit) - Add DKL PHY PLL calculations (Lucas, Vandita, Jose) - Add memory type decoding for bandwidth checking (James) </TIGERLAKE ENABLING> - Downgrade Gen7 and Cherryview back to aliasing-ppGTT (Chris) - Limit MST to <= 8bpc once again (Ville) - Restrict the aliasing-ppgtt to the size of the ggtt (Chris) - Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for SKL+ (Chris, Jason) - Whitelist COMMON_SLICE_CHICKEN2 (Kenneth) - Include GTT page-size info in error state (Matt A) - Clear STOP_RING bit on reset (Chris) - Ignore lost CSB completion events (Chris) - Use a high priority wq for nonblocking plane updates (Ville) - Bump up Skylake/Icelake+ display/plane/fb size restrictions (Manasi, Ville) - Update Gen11/Gen12 forcewake ranges from BSpec (Mika, Daniele, Michel) - Allow downscale factor of <3.0 on GLK+ for all formats (Ville) - Add missing Comet Lake PCH PCI ID (Matt) - Fix Gen11 SFC reset flow (Daniele) - Fix YCbCr programming for ILK-IVB,HSW+ (Ville) - Save audio frequency programming state at audio domain suspend (Kai) - Fix DisplayPort DSC BPP calculations (Maarten) - Add hardware readout for FEC (Maarten) - Do not add all planes when checking scalers on GLK+ (Maarten) - Make small joiner RAM buffer size platform-specific (Matt R) - Use per-process HWSP as scratch (Michal Wi) - Match allowed Gen11+ CDCLK values to BSpec (Matt R) - Rework CDCLK code for clarity and table format (Matt R) - Unify CDCLK code to reuse functions (Ville) - Enhance CDCLK sanitization (Matt R) - Preallocate Braswell top-level page directory (Chris) - Make vgpu ppgtt notificaiton as atomic operation (Xiaolin) - Use NOEVICT for first pass on attemping to pin a GGTT mmap (Chris) - Disable PSR if more than one eDP panel is present (Jose) - Make breadcrumb flushes more robust (Chris) - Extend non readable MCR range (Mika) - Protect our local workers against I915_FENCE_TIMEOUT (Chris) - Allow stolen memory (and future local memory) addresses in sg_table (Matt A) - Better organize the disable sequence in atomic_commit_tail() (Manasi) - Fix regression with crtc disable ordering (Maarten) - Add HW Gamma LUT readout (Swati) - Hook up power management code to use intel_gt (Andi) - Rework codebase towards use of intel_gt (Tvrtko) - Remove incorrect BUG_ON for schedule-out (Chris, Vinay) - Cleanup cache coloring code (Matt A) - Flush writes before RING_TAIL update on SNB (Chris) - Perform GGTT restore much earlier during resume (Chris) - Make shrink pinning atomic (Chris) - Make i915_vma.flags atomic for mutex reduction (Chris) - Make sure the gen6 ppgtt is bound before first use without struct mutex (Chris) - Report IOMMU status in debugfs (Chris) - Disable FBC if BIOS reserved memory (stolen) is unavailable (Chris) - Add a paranoid flushes and context reload around GPU reset (Chris) - Skip engine busyness sampling when and where not needed (Tvrtko) - Use GT parked time for estimating RC6 while asleep (Chris) - Get the correct wakeref for reading hotplug registers from debugfs (Arkadiusz) - Only apply a rmw mmio update if the value changes (Chris, Daniele) - Extend Haswell GT1 PSMI workaround to all HSW (Chris) - Only enqueue already completed requests (Chris) - Fix preempt-to-busy interactions of virtual requests (Chris) - Prevent bonded requests from overtaking each other on preemption (Chris) - Mark contents as dirty on a write fault (Chris) - Adjust length of MI_LOAD_REGISTER_REG (Michal Wi) - Don't disable interrupts for intel_engine_breadcrumbs_irq() (Sebastian) - Extract GT render sleep (rc6) management (Andi) - Rework SSEU reporting code (Stuart) - Use correct DSC registers in intel_configure_pps_for_dsc_encoder (Manasi) - Use enum pipe instead of crtc index to track active pipes (Ville) - Enforce irq-off lockdep check for for timeline locks (Chris) - Flush the existing fence before GGTT read/write (Chris) - Keep drm_i915_file_private around under RCU (Chris) - Call dma_set_max_seg_size() to silence spurious warnings (Lyude) - Make engine's batch pool safe for use with virtual engines (Chris) - Align power domain names with port names (Imre) - Parameterize and unify HPD code (Lucas) - Use RCU for unlocked vm_idr lookup (Chris) - Replace obj->pin_global with obj->frontbuffer (Chris) - Rework code to use INTEL_NUM_PIPES() (Jani) - Convert device info num_pipes to pipe_mask (Jani) - Introduce INTEL_DISPLAY_ENABLED() (Jani) - Stop conflating HAS_DISPLAY() and disabled display (Jani) - Modularize i915 modesetting probing/init code (Jani) - Use drm_format_info_is_yuv_semiplanar() instead of rolling own (Ville) - Other display codebase cleanups (Ville) - Other GEM codebase cleanup, lockdep and selftest improvements (Chris) - Future-proof DDC pin mapping to reuse ICP variant (Matt R) - Rewrite timeline handling to be RCU based (Chris) - Define explicit wedged on init reset state (Michal Wi) - Add GuC firmware for Elkhartlake (Daniele) - Update HuC firmware naming convention and bump versions (Anusha) - Extract common code from GuC stop/disable comm (Fernando) - Fix perf kernel-doc formatting for struct members (Anna) - Documentation fixes (Joonas) The following changes since commit be91233b1053d9725d3a437e3da44ccff2639477: drm/i915: Update DRIVER_DATE to 20190822 (2019-08-22 05:46:28 -0700) are available in the Git repository at: git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2019-10-07 for you to fetch changes up to 9445ad17109b6fe7864acc33f0c62bd9d866b722: drm/i915: Update DRIVER_DATE to 20191007 (2019-10-07 15:24:47 +0300) ---------------------------------------------------------------- UAPI Changes: - Never allow userptr into the mappable GGTT (Chris) No existing users. Avoid anyone from even trying to spare a deadlock scenario. Cross-subsystem Changes: Core Changes: Driver Changes: - Eliminate struct_mutex use as BKL! (Chris) Only used for execbuf serialisation. - Initialize DDI TC and TBT ports (D-I) on Tigerlake (Lucas) - Fix DKL link training for 2.7GHz and 1.62GHz (Jose) - Add Tigerlake DKL PHY programming sequences (Clinton) - Add Tigerlake Thunderbolt PLL divider values (Imre) - drm/i915: Use helpers for drm_mm_node booleans (Chris) - Restrict L3 remapping sysfs interface to dwords (Chris) - Fix audio power up sequence for gen10+ display (Kai) - Skip redundant execlist resubmission (Chris) - Only unwedge if we can reset GPU first (Chris) - Initialise breadcrumb lists on the virtual engine (Chris) - Don't rely on kernel context existing during early errors (Matt A) - Update Icelake+ MG_DP_MODE programming table (Clinton) - Update DMC firmware for Icelake (Anusha) - Downgrade DP MST error after unplugging TypeC cable (Srinivasan) - Limit MST modes based on plane size too (Ville) - Polish intel_tv_mode_valid() (Ville) - Fix g4x sprite scaling stride check with GTT remapping (Ville) - Don't advertize non-exisiting crtcs (Ville) - Clean up encoder->crtc_mask setup (Ville) - Use tc_port instead of port parameter to MG registers (Jose) - Remove static variable for aux last status (Jani) - Implement a better i945gm vblank irq vs. C-states workaround (Ville) - Make the object creation interface consistent (CQ) - Rename intel_vga_msr_write() to intel_vga_reset_io_mem() (Jani, Ville) - Eliminate previous drm_dbg/drm_err usage (Jani) - Move gmbus setup down to intel_modeset_init() (Jani) - Abstract all vgaarb access to intel_vga.[ch] (Jani) - Split out i915_switcheroo.[ch] from i915_drv.c (Jani) - Use intel_gt in has_reset* (Chris) - Eliminate return value for i915_gem_init_early (Matt A) - Selftest improvements (Chris) - Update HuC firmware header version number format (Daniele) ---------------------------------------------------------------- Andi Shyti (2): drm/i915: Hook up GT power management drm/i915: Extract GT render sleep (rc6) management Animesh Manna (9): drm/i915/dsb: feature flag added for display state buffer. drm/i915/dsb: DSB context creation. drm/i915/dsb: Indexed register write function for DSB. drm/i915/dsb: Check DSB engine status. drm/i915/dsb: functions to enable/disable DSB engine. drm/i915/dsb: function to trigger workload execution of DSB. drm/i915/dsb: Enable gamma lut programming using DSB. drm/i915/dsb: Enable DSB for gen12. drm/i915/dsb: Documentation for DSB. Ankit Nautiyal (1): drm/i915: Add Pipe D cursor ctrl register for Gen12 Anna Karas (1): drm/i915/perf: Fix use of kernel-doc format in structure members Anusha Srivatsa (3): drm/dp/dsc: Add Support for all BPCs supported by TGL drm/i915/uc: Update HuC firmware naming convention and load latest HuC drm/i915/dmc: Update ICL DMC version to v1.09 Arkadiusz Hiler (1): drm/i915: Get the correct wakeref for reading HOTPLUG_EN et al. CQ Tang (1): drm/i915/stolen: make the object creation interface consistent Chris Wilson (108): drm/i915: Hold irq-off for the entire fake lock period drm/i915/gtt: Preallocate Braswell top-level page directory drm/i915: Flush the existing fence before GGTT read/write drm/i915: Keep drm_i915_file_private around under RCU drm/i915/selftests: Teach igt_gpu_fill_dw() to take intel_context drm/i915/selftests: Add the usual batch vma managements to st_workarounds drm/i915: Use NOEVICT for first pass on attemping to pin a GGTT mmap drm/i915/selftests: Markup impossible error pointers drm/i915: Only activate i915_active debugobject once drm/i915: Make engine's batch pool safe for use with virtual engines drm/i915/selftests: Remove accidental serialization between gpu_fill drm/i915/selftests: Try to recycle context allocations drm/i915/execlists: Flush the post-sync breadcrumb write harder drm/i915/selftests: Ignore coherency failures on Broadwater drm/i915: Protect our local workers against I915_FENCE_TIMEOUT drm/i915/selftests: cond_resched() within the longer buddy tests drm/i915/execlists: Try rearranging breadcrumb flush drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt drm/i915/gtt: Downgrade Cherryview back to aliasing-ppgtt drm/i915: Remove ppgtt->dirty_engines drm/i915: Use RCU for unlocked vm_idr lookup drm/i915/perf: Assert locking for i915_init_oa_perf_state() drm/i915: Restrict the aliasing-ppgtt to the size of the ggtt drm/i915: Report aliasing ppgtt size as ggtt size drm/i915: Replace obj->pin_global with obj->frontbuffer drm/i915/selftests: Remove unused __engines_name() drm/i915: Refresh the errno to vmf_fault translations drm/i915: Restore relaxed padding (OCL_OOB_SUPPRES_ENABLE) for skl+ drm/i915: Protect debugfs per_file_stats with RCU lock drm/i915/execlists: Remove incorrect BUG_ON for schedule-out drm/i915/execlists: Clear STOP_RING bit on reset drm/i915/execlists: Ignore lost completion events drm/i915/ringbuffer: Flush writes before RING_TAIL update drm/i915: Perform GGTT restore much earlier during resume drm/i915/selftests: Take runtime wakeref for igt_ggtt_lowlevel drm/i915/selftests: Tighten the timeout testing for partial mmaps drm/i915/tgl: Disable rc6 for debugging drm/i915: Make shrink/unshrink be atomic drm/i915: Make i915_vma.flags atomic_t for mutex reduction drm/i915/display: Add glk_cdclk_table drm/i915/tgl: Disable read-only ppgtt support drm/i915: Squeeze iommu status into debugfs/i915_capabilities drm/i915: Disable FBC if BIOS reserved memory (stolen) is unavailable drm/i915/execlists: Add a paranoid flush of the CSB pointers upon reset drm/i915/execlists: Ensure the context is reloaded after a GPU reset drm/i915/pmu: Use GT parked for estimating RC6 while asleep drm/i915/tgl: Disable preemption while being debugged drm/i915/selftests: Keep the engine awake while we keep for preemption drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use drm/i915: Don't mix srcu tag and negative error codes drm/i915/tgl: Limit ourselves to just rcs0 drm/i915: Show the logical context ring state on dumping drm/i915: Only apply a rmw mmio update if the value changes drm/i915/tgl: Extend MI_SEMAPHORE_WAIT drm/i915: Extend Haswell GT1 PSMI workaround to all drm/i915: Verify the engine after acquiring the active.lock drm/i915/selftests: Exercise CS TLB invalidation drm/i915/tgl: Suspend pre-parser across GTT invalidations drm/i915: Mark i915_request.timeline as a volatile, rcu pointer drm/i915: Lock signaler timeline while navigating drm/i915: Protect timeline->hwsp dereferencing Revert "drm/i915/tgl: Implement Wa_1406941453" drm/i915/execlists: Relax assertion for a pinned context image on reset drm/i915/execlists: Drop redundant list_del_init(&rq->sched.link) drm/i915: Only enqueue already completed requests drm/i915/execlists: Refactor -EIO markup of hung requests drm/i915: Fixup preempt-to-busy vs resubmission of a virtual request drm/i915: Fixup preempt-to-busy vs reset of a virtual request drm/i915: Prevent bonded requests from overtaking each other on preemption drm/i915: Mark contents as dirty on a write fault drm/i915/selftests: Verify the LRC register layout between init and HW drm/i915/tgl: Swap engines for no rps (gpu reclocking) drm/i915/execlists: Simplify gen12_csb_parse drm/i915/selftests: Exercise concurrent submission to all engines drm/i915/selftests: Do not try to sanitize mock HW drm/i915: Pass intel_gt to has-reset? drm/i915/selftests: Distinguish mock device from no wakeref drm/i915/selftests: Provide a mock GPU reset routine drm/i915/selftests: Exercise context switching in parallel drm/i915/gt: Only unwedge if we can reset first drm/i915: Initialise breadcrumb lists on the virtual engine drm/i915/userptr: Never allow userptr into the mappable GGTT drm/i915/selftests: Extract random_offset() for use with a prng drm/i915/gem: Refactor tests on obj->ops->flags drm/i915/selftests: Exercise potential false lite-restore drm/i915/execlists: Skip redundant resubmission drm/i915: Restrict L3 remapping sysfs interface to dwords drm/i915: Use helpers for drm_mm_node booleans drm/i915: Only track bound elements of the GTT drm/i915: Mark up address spaces that may need to allocate drm/i915: Pull i915_vma_pin under the vm->mutex drm/i915: Push the i915_active.retire into a worker drm/i915: Coordinate i915_active with its own mutex drm/i915: Move idle barrier cleanup into engine-pm drm/i915: Drop struct_mutex from around i915_retire_requests() drm/i915: Remove the GEM idle worker drm/i915: Merge wait_for_timelines with retire_request drm/i915/gem: Retire directly for mmap-offset shrinking drm/i915: Move request runtime management onto gt drm/i915: Move global activity tracking from GEM to GT drm/i915: Remove logical HW ID drm/i915: Move context management under GEM drm/i915/overlay: Drop struct_mutex guard drm/i915: Drop struct_mutex guard from debugfs/framebuffer_info drm/i915: Remove struct_mutex guard for debugfs/opregion drm/i915: Drop struct_mutex from suspend state save/restore drm/i915/selftests: Drop vestigal struct_mutex guards drm/i915: Drop struct_mutex from around GEM initialisation Clinton A Taylor (4): drm/i915/tgl: Add missing ddi clock select during DP init sequence drm/i915/tgl/pll: Set update_active_dpll drm/i915/tc: Update DP_MODE programming drm/i915/tgl: Add dkl phy programming sequences Daniel Vetter (1): drm/i915: disable set/get_tiling ioctl on gen12+ Daniele Ceraolo Spurio (5): drm/i915/uc: define GuC and HuC FWs for EHL drm/i915: use a separate context for gpu relocs drm/i915: fix SFC reset flow drm/i915/tgl: s/ss/eu fuse reading support drm/i915/huc: fix version parsing from CSS header Dhinakaran Pandiyan (1): drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Fernando Pacheco (1): drm/i915/uc: Extract common code from GuC stop/disable comm Imre Deak (2): drm/i915: Align power domain names with port names drm/i915/tgl: Add the Thunderbolt PLL divider values James Ausmus (1): drm/i915/tgl: Add memory type decoding for bandwidth checking Jani Nikula (18): drm/i915: add INTEL_NUM_PIPES() and use it drm/i915: convert device info num_pipes to pipe_mask drm/i915: introduce INTEL_DISPLAY_ENABLED() drm/i915: stop conflating HAS_DISPLAY() and disabled display drm/i915/dsb: single register write function for DSB. drm/i915: add i915_driver_modeset_remove() drm/i915: pass i915 to i915_driver_modeset_probe() drm/i915: pass i915 to intel_modeset_driver_remove() drm/i915: abstract intel_panel_sanitize_ssc() from intel_modeset_init() drm/i915: abstract intel_mode_config_init() from intel_modeset_init() drm/i915: pass i915 to intel_modeset_init() and intel_modeset_init_hw() drm/i915/display: abstract all vgaarb access to intel_vga.[ch] drm/i915: use DRM_ERROR() instead of drm_err() drm/i915: use DRM_DEBUG_KMS() instead of drm_dbg(DRM_UT_KMS, ...) drm/i915/dp: remove static variable for aux last status drm/i915/vga: rename intel_vga_msr_write() to intel_vga_reset_io_mem() drm/i915: split out i915_switcheroo.[ch] from i915_drv.c drm/i915: move gmbus setup down to intel_modeset_init() Joonas Lahtinen (4): drm/i915: Remove link to missing "Batchbuffer Pools" documentation drm/i915: Indent GuC/WOPCM documentation sections drm/i915: Update DRIVER_DATE to 20190927 drm/i915: Update DRIVER_DATE to 20191007 José Roberto de Souza (21): drm/i915/psr: Make PSR registers relative to transcoders drm/i915: Add transcoder restriction to PSR2 drm/i915: Do not unmask PSR interruption in IRQ postinstall drm/i915/tgl: Guard and warn if more than one eDP panel is present drm/i915: Do not read PSR2 register in transcoders without PSR2 drm/i915/tgl: Add maximum resolution supported by PSR2 HW drm: Add for_each_oldnew_intel_crtc_in_state_reverse() drm/i915: Disable pipes in reverse order drm/i915/tgl: Implement TGL DisplayPort training sequence drm/i915/tgl: PSR link standby is not supported anymore drm/i915/psr: Only handle interruptions of the transcoder in use drm/i915/tgl: Access the right register when handling PSR interruptions drm/i915: Apply FBC WA for TGL too drm/i915/mst: Do not hardcoded the crtcs that encoder can connect drm/i915/tgl: Finish modular FIA support on registers drm/i915/icl: Unify disable and enable phy clock gating functions drm/i915/tgl: Check the UC health of tc controllers after power on drm/i915/tgl: Add dkl phy pll calculations drm/i915/tgl: Return the mg/dkl pll as DDI clock for new TC ports drm/i915/tgl: Fix dkl link training drm/i915/mg: Use tc_port instead of port parameter to MG registers Kai Vehmanen (3): drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend drm/i915: Fix audio power up sequence for gen10+ display drm/i915: extend audio CDCLK>=2*BCLK constraint to more platforms Kenneth Graunke (1): drm/i915: Whitelist COMMON_SLICE_CHICKEN2 Lucas De Marchi (11): drm/i915: parameterize south hpd macros drm/i915: unify icp, tgp and mcc irq handling drm/i915: parameterize SDE hotplug registers drm/i915: unify icp, tgp and mcc irq setup drm/i915: protect access to DP_TP_* on non-dp drm/i915/tgl: move DP_TP_* to transcoder drm/i915/tgl: disable SAGV temporarily drm/i915/tgl: add gen12 to stolen initialization drm/i915/tgl: Add initial dkl pll support drm/i915/tgl: re-indent code to prepare for DKL changes drm/i915/tgl: initialize TC and TBT ports Lyude Paul (1): drm/i915: Call dma_set_max_seg_size() in i915_driver_hw_probe() Maarten Lankhorst (6): drm/i915: Fix regression with crtc disable ordering drm/i915/dp: Fix dsc bpp calculations, v5. drm/i915: Add hardware readout for FEC drm/i915: Get rid of crtc_state->fb_changed drm/i915: Rename planar linked plane variables drm/i915: Do not add all planes when checking scalers on glk+ Madhumitha Tolakanahalli Pradeep (1): drm/i915/tgl: Enabling DSC on Pipe A for TGL Manasi Navare (5): drm/i915/dp: Fix DSC enable code to use cpu_transcoder instead of encoder->type drm/i915/display: Rename update_crtcs() to commit_modeset_enables() drm/i915/display: Move the commit_tail() disable sequence to separate function drm/i915/display/icl: Bump up the hdisplay and vdisplay as per transcoder limits drm/i915/display/icl: Bump up the plane/fb height Matt Roper (15): drm/i915: Allow /2 CD2X divider on gen11+ drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+ drm/i915/tgl: Use refclk/2 as bypass frequency drm/i915: Consolidate bxt/cnl/icl cdclk readout drm/i915: Use literal representation of cdclk tables drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk drm/i915: Kill cnl_sanitize_cdclk() drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk drm/i915: Add calc_voltage_level display vfunc drm/i915: Enhance cdclk sanitization drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk drm/i915/cml: Add second PCH ID for CMP drm/i915: Future-proof DDC pin mapping drm/i915: Unify ICP and MCC hotplug pin tables drm/i915: Small joiner RAM buffer size is platform-specific Matthew Auld (8): drm/i915: s/for_each_sgt_dma/for_each_sgt_daddr/ drm/i915/buddy: add missing call to i915_global_register drm/i915: export color_differs drm/i915: s/i915_gtt_color_adjust/i915_ggtt_color_adjust drm/i915: cleanup cache-coloring drm/i915: include GTT page-size info in error state drm/i915: check for kernel_context drm/i915: simplify i915_gem_init_early Michał Winiarski (4): drm/i915: Define explicit wedged on init reset state drm/i915/execlists: Use per-process HWSP as scratch drm/i915: Adjust length of MI_LOAD_REGISTER_REG drm/i915: Add definitions for MI_MATH command Michel Thierry (7): drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards drm/i915/tgl/perf: use the same oa ctx_id format as icl drm/i915/tgl: Register state context definition for Gen12 drm/i915/tgl: Introduce gen12 forcewake ranges drm/i915/tgl: Implement Wa_1406941453 Mika Kuoppala (4): drm/i915: Extend non readable mcr range drm/i915: Use engine relative LRIs on context setup drm/i915: Update Gen11 forcewake ranges drm/i915/tgl: Re-enable rc6 Radhakrishna Sripada (1): drm/i915/tgl: Implement Wa_1409142259 Ramalingam C (6): drm/i915: mei_hdcp: I915 sends ddi index as per ME FW drm: Move port definition back to i915 header drm: Extend I915 mei interface for transcoder info misc/mei/hdcp: Fill transcoder index in port info drm/i915/hdcp: update current transcoder into intel_hdcp drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+ Sebastian Andrzej Siewior (2): drm/i915: Drop the IRQ-off asserts drm/i915: Don't disable interrupts for intel_engine_breadcrumbs_irq() Srinivasan S (1): drm/i915/dp: Fix DP MST error after unplugging TypeC cable Stanislav Lisovskiy (1): drm/i915: Add TigerLake bandwidth checking Stuart Summers (11): drm/i915: Use variable for debugfs device status drm/i915: Add function to set SSEU info per platform drm/i915: Add subslice stride runtime parameter drm/i915: Add EU stride runtime parameter drm/i915: Use local variables for subslice_mask for device info drm/i915: Add function to set subslices drm/i915: Use subslice stride to set subslices for a given slice drm/i915: Add function to determine if a slice has a subslice drm/i915: Refactor instdone loops on new subslice functions drm/i915: Add new function to copy subslices for a slice drm/i915: Expand subslice mask Swati Sharma (13): drm/i915/display: Add debug log for color parameters drm/i915/display: Add func to get gamma bit precision drm/i915/display: Add func to compare hw/sw gamma lut drm/i915/display: Add macro to compare gamma hw/sw lut drm/i915/display: Extract i9xx_read_luts() drm/i915/display: Extract ilk_read_luts() drm/i915/display: Extract glk_read_luts() drm/i915/display: Add gamma precision function for CHV drm/i915/display: Extract i965_read_luts() drm/i915/display: Extract chv_read_luts() drm/i915/color: Fix formatting issues drm/i915/color: Extract icl_read_luts() Revert "drm/i915/color: Extract icl_read_luts()" Tvrtko Ursulin (5): drm/i915: Move GT init to intel_gt.c drm/i915: Make wait_for_timelines take struct intel_gt drm/i915: Avoid round-trip via i915 in intel_gt_park drm/i915: Make pm_notify take intel_gt drm/i915/pmu: Skip busyness sampling when and where not needed Vandita Kulkarni (2): drm/i915/tgl: Add dkl phy registers drm/i915/tgl: Add support for dkl pll write Ville Syrjälä (38): drm/i915: Use enum pipe instead of crtc index to track active pipes drm/i915: Unconfuse pipe vs. crtc->index in i915_get_crtc_scanoutpos() drm/i915: Use enum pipe consistently drm/i915: s/num_active_crtcs/num_active_pipes/ drm/i915: Use hweight8() for 8bit masks drm/i915: Limit MST to <= 8bpc once again drm/i915: Prefer encoder->name over port_name() drm/i915: Clean up HDMI deep color handling a bit Revert "drm/i915: Fix DP-MST crtc_mask" drm/i915: add immutable zpos plane properties drm/i915: Use a high priority wq for nonblocking plane updates drm/i915: Remove pointless planes_changed=true assignment drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk drm/i915: Fix CD2X pipe select masking during cdclk sanitation drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+ drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs drm/i915: Replace is_planar_yuv_format() with drm_format_info_is_yuv_semiplanar() drm/i915: Allow downscale factor of <3.0 on glk+ for all formats drm/i915: Extract intel_modeset_calc_cdclk() drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check() drm/i915: Bump skl+ max plane width to 5k for linear/x-tiled drm/i915: Don't advertise modes that exceed the max plane size drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication drm/i915: Fix AVI infoframe quantization range for YCbCr output drm/i915: Extract intel_hdmi_limited_color_range() drm/i915: Never set limited_color_range=true for YCbCr output drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout drm/i915: Simplify intel_get_crtc_ycbcr_config() drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW drm/i915: Document ILK+ pipe csc matrix better drm/i915: Set up ILK/SNB csc unit properly for YCbCr output drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB drm/i915: Limit MST modes based on plane size too drm/i915: Polish intel_tv_mode_valid() drm/i915: Fix g4x sprite scaling stride check with GTT remapping drm/i915: Populate possible_crtcs correctly drm/i915: Clean up encoder->crtc_mask setup drm/i915: Implement a better i945gm vblank irq vs. C-states workaround Xiaolin Zhang (1): drm/i915: to make vgpu ppgtt notificaiton as atomic operation Documentation/gpu/i915.rst | 32 +- drivers/gpu/drm/i915/Makefile | 7 +- drivers/gpu/drm/i915/display/intel_atomic.c | 24 +- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 9 +- drivers/gpu/drm/i915/display/intel_audio.c | 36 +- drivers/gpu/drm/i915/display/intel_bios.c | 2 +- drivers/gpu/drm/i915/display/intel_bios.h | 3 +- drivers/gpu/drm/i915/display/intel_bw.c | 81 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 1264 ++++++++------------ drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +- drivers/gpu/drm/i915/display/intel_color.c | 529 +++++++- drivers/gpu/drm/i915/display/intel_color.h | 7 + drivers/gpu/drm/i915/display/intel_crt.c | 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 642 +++++++--- drivers/gpu/drm/i915/display/intel_display.c | 1101 +++++++++-------- drivers/gpu/drm/i915/display/intel_display.h | 51 +- drivers/gpu/drm/i915/display/intel_display_power.c | 398 +++--- drivers/gpu/drm/i915/display/intel_display_power.h | 40 +- drivers/gpu/drm/i915/display/intel_display_types.h | 36 +- drivers/gpu/drm/i915/display/intel_dp.c | 408 ++++--- drivers/gpu/drm/i915/display/intel_dp.h | 7 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 30 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 364 +++++- drivers/gpu/drm/i915/display/intel_dsb.c | 332 +++++ drivers/gpu/drm/i915/display/intel_dsb.h | 52 + drivers/gpu/drm/i915/display/intel_dsi.c | 3 +- drivers/gpu/drm/i915/display/intel_dvo.c | 4 +- drivers/gpu/drm/i915/display/intel_fbc.c | 7 +- drivers/gpu/drm/i915/display/intel_fbdev.c | 14 +- drivers/gpu/drm/i915/display/intel_frontbuffer.c | 19 +- drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 214 +++- drivers/gpu/drm/i915/display/intel_hdcp.h | 4 + drivers/gpu/drm/i915/display/intel_hdmi.c | 229 ++-- drivers/gpu/drm/i915/display/intel_hdmi.h | 1 + drivers/gpu/drm/i915/display/intel_hotplug.c | 3 +- drivers/gpu/drm/i915/display/intel_hotplug.h | 1 + drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +- drivers/gpu/drm/i915/display/intel_lvds.c | 8 +- drivers/gpu/drm/i915/display/intel_overlay.c | 31 +- drivers/gpu/drm/i915/display/intel_psr.c | 299 +++-- drivers/gpu/drm/i915/display/intel_psr.h | 1 - drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.h | 1 + drivers/gpu/drm/i915/display/intel_sprite.c | 122 +- drivers/gpu/drm/i915/display/intel_sprite.h | 1 - drivers/gpu/drm/i915/display/intel_tc.c | 87 +- drivers/gpu/drm/i915/display/intel_tc.h | 1 + drivers/gpu/drm/i915/display/intel_tv.c | 10 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +- drivers/gpu/drm/i915/display/intel_vga.c | 160 +++ drivers/gpu/drm/i915/display/intel_vga.h | 18 + drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_client_blt.c | 9 +- drivers/gpu/drm/i915/gem/i915_gem_context.c | 390 ++---- drivers/gpu/drm/i915/gem/i915_gem_context.h | 42 +- drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 20 +- drivers/gpu/drm/i915/gem/i915_gem_domain.c | 56 +- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 83 +- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 101 +- drivers/gpu/drm/i915/gem/i915_gem_object.c | 33 +- drivers/gpu/drm/i915/gem/i915_gem_object.h | 29 +- drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 8 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 1 + drivers/gpu/drm/i915/gem/i915_gem_pm.c | 150 +-- drivers/gpu/drm/i915/gem/i915_gem_shrinker.c | 124 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 62 +- drivers/gpu/drm/i915/gem/i915_gem_throttle.c | 4 +- drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 34 +- drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 31 +- drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 163 +-- .../drm/i915/gem/selftests/i915_gem_coherency.c | 40 +- .../gpu/drm/i915/gem/selftests/i915_gem_context.c | 540 ++++++--- drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 268 ++++- .../drm/i915/gem/selftests/i915_gem_object_blt.c | 4 - drivers/gpu/drm/i915/gem/selftests/i915_gem_phys.c | 2 - drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c | 33 +- drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h | 13 +- drivers/gpu/drm/i915/gem/selftests/mock_context.c | 15 +- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 19 +- drivers/gpu/drm/i915/gt/intel_context.c | 22 +- drivers/gpu/drm/i915/gt/intel_context_types.h | 1 + drivers/gpu/drm/i915/gt/intel_engine.h | 1 - drivers/gpu/drm/i915/gt/intel_engine_cs.c | 73 +- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 44 +- drivers/gpu/drm/i915/gt/intel_engine_pool.c | 15 +- drivers/gpu/drm/i915/gt/intel_engine_pool.h | 4 +- drivers/gpu/drm/i915/gt/intel_engine_types.h | 35 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 30 +- drivers/gpu/drm/i915/gt/intel_gt.c | 149 ++- drivers/gpu/drm/i915/gt/intel_gt.h | 12 +- drivers/gpu/drm/i915/gt/intel_gt_pm.c | 85 +- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 11 + drivers/gpu/drm/i915/gt/intel_gt_requests.c | 123 ++ drivers/gpu/drm/i915/gt/intel_gt_requests.h | 24 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 18 +- drivers/gpu/drm/i915/gt/intel_hangcheck.c | 5 +- drivers/gpu/drm/i915/gt/intel_lrc.c | 1240 +++++++++++++------ drivers/gpu/drm/i915/gt/intel_lrc.h | 14 + drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 66 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 712 +++++++++++ drivers/gpu/drm/i915/gt/intel_rc6.h | 25 + drivers/gpu/drm/i915/gt/intel_rc6_types.h | 28 + drivers/gpu/drm/i915/gt/intel_reset.c | 140 ++- drivers/gpu/drm/i915/gt/intel_reset.h | 16 +- drivers/gpu/drm/i915/gt/intel_reset_types.h | 6 + drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 99 +- drivers/gpu/drm/i915/gt/intel_sseu.c | 37 +- drivers/gpu/drm/i915/gt/intel_sseu.h | 37 +- drivers/gpu/drm/i915/gt/intel_timeline.c | 56 +- drivers/gpu/drm/i915/gt/intel_timeline_types.h | 10 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +- drivers/gpu/drm/i915/gt/selftest_context.c | 62 +- drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 50 + drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 155 +-- drivers/gpu/drm/i915/gt/selftest_lrc.c | 513 +++++--- drivers/gpu/drm/i915/gt/selftest_reset.c | 4 +- drivers/gpu/drm/i915/gt/selftest_timeline.c | 97 +- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 63 +- drivers/gpu/drm/i915/gt/selftests/mock_timeline.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 3 + drivers/gpu/drm/i915/gt/uc/intel_uc.c | 30 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 51 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 8 +- drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 4 - drivers/gpu/drm/i915/gvt/aperture_gm.c | 12 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/gvt/kvmgt.c | 17 - drivers/gpu/drm/i915/gvt/scheduler.c | 27 +- drivers/gpu/drm/i915/i915_active.c | 340 ++++-- drivers/gpu/drm/i915/i915_active.h | 328 ++--- drivers/gpu/drm/i915/i915_active_types.h | 33 +- drivers/gpu/drm/i915/i915_buddy.c | 1 + drivers/gpu/drm/i915/i915_debugfs.c | 274 +++-- drivers/gpu/drm/i915/i915_drv.c | 212 ++-- drivers/gpu/drm/i915/i915_drv.h | 119 +- drivers/gpu/drm/i915/i915_gem.c | 317 +---- drivers/gpu/drm/i915/i915_gem_evict.c | 58 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 9 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 259 ++-- drivers/gpu/drm/i915/i915_gem_gtt.h | 67 +- drivers/gpu/drm/i915/i915_getparam.c | 4 +- drivers/gpu/drm/i915/i915_gpu_error.c | 28 +- drivers/gpu/drm/i915/i915_gpu_error.h | 3 +- drivers/gpu/drm/i915/i915_irq.c | 322 ++--- drivers/gpu/drm/i915/i915_irq.h | 4 +- drivers/gpu/drm/i915/i915_pci.c | 44 +- drivers/gpu/drm/i915/i915_perf.c | 116 +- drivers/gpu/drm/i915/i915_perf.h | 5 +- drivers/gpu/drm/i915/i915_pmu.c | 247 ++-- drivers/gpu/drm/i915/i915_pmu.h | 4 +- drivers/gpu/drm/i915/i915_query.c | 10 +- drivers/gpu/drm/i915/i915_reg.h | 636 +++++++--- drivers/gpu/drm/i915/i915_request.c | 276 ++--- drivers/gpu/drm/i915/i915_request.h | 32 +- drivers/gpu/drm/i915/i915_scatterlist.h | 8 +- drivers/gpu/drm/i915/i915_suspend.c | 11 +- drivers/gpu/drm/i915/i915_switcheroo.c | 67 ++ drivers/gpu/drm/i915/i915_switcheroo.h | 14 + drivers/gpu/drm/i915/i915_sysfs.c | 88 +- drivers/gpu/drm/i915/i915_trace.h | 40 +- drivers/gpu/drm/i915/i915_vgpu.c | 1 + drivers/gpu/drm/i915/i915_vma.c | 590 ++++++--- drivers/gpu/drm/i915/i915_vma.h | 132 +- drivers/gpu/drm/i915/intel_csr.c | 4 +- drivers/gpu/drm/i915/intel_device_info.c | 217 ++-- drivers/gpu/drm/i915/intel_device_info.h | 3 +- drivers/gpu/drm/i915/intel_pch.c | 1 + drivers/gpu/drm/i915/intel_pch.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 906 ++------------ drivers/gpu/drm/i915/intel_pm.h | 3 - drivers/gpu/drm/i915/intel_runtime_pm.c | 1 - drivers/gpu/drm/i915/intel_uncore.c | 94 +- drivers/gpu/drm/i915/intel_uncore.h | 20 +- drivers/gpu/drm/i915/selftests/i915_active.c | 42 +- drivers/gpu/drm/i915/selftests/i915_buddy.c | 4 + drivers/gpu/drm/i915/selftests/i915_gem.c | 12 +- drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 55 +- drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 395 +++++- .../gpu/drm/i915/selftests/i915_live_selftests.h | 2 + drivers/gpu/drm/i915/selftests/i915_random.c | 20 + drivers/gpu/drm/i915/selftests/i915_random.h | 4 + drivers/gpu/drm/i915/selftests/i915_request.c | 251 ++-- drivers/gpu/drm/i915/selftests/i915_selftest.c | 8 +- drivers/gpu/drm/i915/selftests/i915_vma.c | 19 +- drivers/gpu/drm/i915/selftests/igt_flush_test.c | 33 +- drivers/gpu/drm/i915/selftests/igt_flush_test.h | 2 +- drivers/gpu/drm/i915/selftests/igt_live_test.c | 14 +- drivers/gpu/drm/i915/selftests/igt_spinner.c | 2 +- drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + drivers/gpu/drm/i915/selftests/mock_gem_device.c | 36 +- drivers/gpu/drm/i915/selftests/mock_gtt.c | 6 +- drivers/misc/mei/hdcp/mei_hdcp.c | 45 +- drivers/misc/mei/hdcp/mei_hdcp.h | 17 +- include/drm/i915_drm.h | 18 - include/drm/i915_mei_hdcp_interface.h | 42 +- include/uapi/drm/i915_drm.h | 6 +- 198 files changed, 12046 insertions(+), 8192 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.c create mode 100644 drivers/gpu/drm/i915/display/intel_dsb.h create mode 100644 drivers/gpu/drm/i915/display/intel_vga.c create mode 100644 drivers/gpu/drm/i915/display/intel_vga.h create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_requests.c create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_requests.h create mode 100644 drivers/gpu/drm/i915/gt/intel_rc6.c create mode 100644 drivers/gpu/drm/i915/gt/intel_rc6.h create mode 100644 drivers/gpu/drm/i915/gt/intel_rc6_types.h create mode 100644 drivers/gpu/drm/i915/gt/selftest_gt_pm.c create mode 100644 drivers/gpu/drm/i915/i915_switcheroo.c create mode 100644 drivers/gpu/drm/i915/i915_switcheroo.h

Message ID	20191007134801.GA24313@jlahtine-desk.ger.corp.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=xUWD=YA=lists.freedesktop.org=dri-devel-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5B13A20867 Date: Mon, 7 Oct 2019 16:48:01 +0300 From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> To: Dave Airlie <airlied@gmail.com>, Daniel Vetter <daniel.vetter@ffwll.ch> Subject: [PULL] drm-intel-next Message-ID: <20191007134801.GA24313@jlahtine-desk.ger.corp.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.12.0 (2019-05-25) Precedence: list Cc: dim-tools@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Maxime Ripard <mripard@kernel.org>, Rodrigo Vivi <rodrigo.vivi@intel.com>, Sean Paul <sean@poorly.run>, intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
Series	[PULL] drm-intel-next \| expand [PULL] drm-intel-next

[PULL] drm-intel-next

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