diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..9bd286ab2bee 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -756,6 +756,124 @@ extern "C" {
  */
 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
 
+/*
+ * AMD GFX9+ format modifiers
+ */
+
+/*
+ * enum-like values for easy switches.
+ *
+ * No fixed field-size but implementations are supposed to enforce all-zeros of
+ * unused bits during validation.
+ */
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_STANDARD_id       0
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_DISPLAY_id        1
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_X_STANDARD_id     2
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_X_DISPLAY_id      3
+#define DRM_FORMAT_MOD_AMD_GFX10_64K_X_RENDER_id      4
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_X_STANDARD_DCC_id 5
+#define DRM_FORMAT_MOD_AMD_GFX10_64K_X_RENDER_DCC_id  6
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_X_DCN1_DCC_id     7
+
+/*
+ * tiling modes that are compatible between all GPUs that support the tiling
+ * mode.
+ *
+ * STANDARD/DISPLAY/ROTATED + bitdepth determine the indexing within a 256 byte
+ * micro-block.
+ *
+ * The macro-block is 64 KiB and the micro-block in macro-block addressing is
+ * y0-x0-y1-x1-... up till the dimensions of the macro-block.
+ *
+ * The image is then a plain row-major image of macro-blocks.
+ */
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_STANDARD \
+	fourcc_mod_code(AMD, DRM_FORMAT_MOD_AMD_GFX9_64K_STANDARD_id)
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_DISPLAY  \
+	fourcc_mod_code(AMD, DRM_FORMAT_MOD_AMD_GFX9_64K_DISPLAY_id)
+
+/*
+ * Same as above, but applies a transformation on the micro-block in macro-block
+ * indexing that depends on the GPU pipes, shader engines and banks.
+ *
+ * RENDER is a new micro-block tiling for GFX10+.
+ */
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_X_STANDARD(family_id, external_rev)  \
+	fourcc_mod_code(AMD, DRM_FORMAT_MOD_AMD_GFX9_64K_X_STANDARD_id | \
+	                     ((uint64_t)family_id << 40) |               \
+	                     ((uint64_t)external_rev << 48))
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_X_DISPLAY(family_id, external_rev)   \
+	fourcc_mod_code(AMD, DRM_FORMAT_MOD_AMD_GFX9_64K_X_DISPLAY_id |  \
+	                     ((uint64_t)family_id << 40) |               \
+	                     ((uint64_t)external_rev << 48))
+#define DRM_FORMAT_MOD_AMD_GFX10_64K_X_RENDER(family_id, external_rev)   \
+	fourcc_mod_code(AMD, DRM_FORMAT_MOD_AMD_GFX10_64K_X_RENDER_id |  \
+	                     ((uint64_t)family_id << 40) |               \
+	                     ((uint64_t)external_rev << 48))
+
+/*
+ * Same as above, but with DCC enabled.
+ *
+ * We add the PCI ID of the device to make sure the transformation above is
+ * applied the same way, as well as make sure the implementation of DCC supports
+ * the same patterns.
+ *
+ * The DCC is pipe-aligned (and on GFX9 rb-aligned).
+ *
+ * This includes 2 memory regions per plane:
+ *  - main image
+ *  - DCC metadata
+ *
+ * These are tightly packed according to platform specific DCC alignment
+ * requirements.
+ *
+ * pipe+rb aligned DCC alignment:
+ * - GFX9: MAX(65536,
+ *             MIN2(32, pipes * shader_engines) *
+ *               num_backends * interleave_bytes)
+ * - GFX10 (without rbplus): MAX2(pipes * interleave_bytes, 4096)
+ *
+ * aligned DCC size:
+ * - GFX9:
+ *    tiles of MAX2(256 * num_backends KiB, 1 MiB) of pixel data (prefer
+ *    width if odd log2) at ratio 1/256
+ * - GFX10 (without rbplus):
+ *    tiles of 256 * MAX2(pipes * interleave_bytes, 4096) of pixel data
+ *    (prefer width if odd log2) at ratio 1/256
+ */
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_X_STANDARD_DCC(family_id, external_rev)  \
+	fourcc_mod_code(AMD, DRM_FORMAT_MOD_AMD_GFX9_64K_X_STANDARD_DCC_id | \
+	                     ((uint64_t)family_id << 40) |                   \
+	                     ((uint64_t)external_rev << 48))
+#define DRM_FORMAT_MOD_AMD_GFX10_64K_X_RENDER_DCC(family_id, external_rev)   \
+	fourcc_mod_code(AMD, DRM_FORMAT_MOD_AMD_GFX10_64K_X_RENDER_DCC_id |  \
+	                     ((uint64_t)family_id << 40) |                   \
+	                     ((uint64_t)external_rev << 48))
+
+/*
+ * DCC that is displayable with DCN1 hardware.
+ *
+ * for bpp <= 32 bits, the micro-tiling is STANDARD and for bpp == 64 bits, the
+ * micro-tiling is DISPLAY.
+ *
+ * This includes 3 memory regions per plane:
+ *   - main image
+ *   - DCC (non aligned)
+ *   - DCC (pipe-aligned & rb-aligned)
+ *
+ * non-aligned DCC alignment:
+ * - GFX9: MAX(65536, interleave_bytes)
+ * - GFX10 (without rbplus): 4096
+ *
+ * non-aligned DCC size:
+ * - GFX9 & GFX10 (without rbplus):
+ *    tiles for 1 MiB of pixel data (prefer width if odd log2) at ratio 1/256
+ */
+#define DRM_FORMAT_MOD_AMD_GFX9_64K_X_DCN1_DCC(family_id, external_rev)  \
+	fourcc_mod_code(AMD, DRM_FORMAT_MOD_AMD_GFX9_64K_X_DCN1_DCC_id | \
+	                     ((uint64_t)family_id << 40) |               \
+	                     ((uint64_t)external_rev << 48))
+
 #if defined(__cplusplus)
 }
 #endif
