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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dKmJ4wpX5ZyFbumc2ifmjqNnf9wJCU29SEpx72Ochtk=; b=yeIYHWEEWa1Ffe4fi83tuBdz2dG7DvJUcboI3DZIUv8lBIvYxmKl7RiRHIngM2PBW55TT1ogrQGRAp9NpZPq53zybrFmPLFZN33AyavMIlQlohEzY5aT4BlbwANOVT+hKJwVGNnFXOd+rEZzDh2uDg1ijB/XbyDQCnlDWxOw9ig= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Rodrigo.Siqueira@amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "amd-gfx@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , "dri-devel@lists.freedesktop.org" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Commit d7cd0e05 introduced a change at DP_DSC_THROUGHPUT_MODE_0_170 which is not aligned with the spec. This commit replace 15 << 4 by 15 << 0 for DP_DSC_THROUGHPUT_MODE_0_170 in order to make it follow the specification. Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: Nikola Cornij Cc: Jani Nikula Cc: Manasi Navare Cc: Ville Syrjälä Fixes: d7cd0e053b1 (drm/amd/display: Add 170Mpix/sec DSC throughput support) Signed-off-by: Rodrigo Siqueira Reviewed-by: Harry Wentland --- include/drm/drm_dp_helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index cfadeeef8492..52024049c59e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -306,7 +306,7 @@ # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 4) +# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 # define DP_DSC_THROUGHPUT_MODE_1_UPSUPPORTED 0