From patchwork Tue Oct 29 13:52:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lipski, Mikita" X-Patchwork-Id: 11217939 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A0D9914DB for ; Tue, 29 Oct 2019 13:53:03 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8764020862 for ; Tue, 29 Oct 2019 13:53:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8764020862 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amd.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 74D996E3A8; Tue, 29 Oct 2019 13:52:59 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-eopbgr820082.outbound.protection.outlook.com [40.107.82.82]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F74E6E354; Tue, 29 Oct 2019 13:52:54 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VbsThFTz9Dy+Z4vnHhQRuACNdbiWK1rnzRWdWNUiuBPbnHRrAhq5Swq68qcLLazsi5uj+Ek1xLulXitQIa37oJxOCVPmWK5OJTmi4ZsBoLCcZIMLpeT3lLaHU/bHmwqQHrK3YjsHhRopjc2i5Q7wTSxuGyPhPIZ43eFWCIcC57wQF9L5U8487Vk4imoWj6ISPIFaYEX9ehGiXZ2gf5+RTtWb++C+e4E/WTYcgA7ybf5ZjRbeXM5WIoo2RTQK7DD3o6GAlG5yobGp2XF8GooDGCx1ko3sHo41VNJnuvDHjOARjaMtmhYBAYu5O4GojQ7/BkEeA765k0YzDxwUF4e33A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jUXd+gNjqKSXAZLjxfZe6ovy4XKjOhe5JAT5Rspt6h0=; b=CSNHhj8UXut3tgDrGjkQAuP+wfhkEIWBZydYX86Lwoo821NTvWK3sAl3eRHfMxmvhNfTgjon1aPbkLecc0TGkSB1tb/OICqboC1K1aOSXJW7k8llcURL9NxnQCKszFm+8fS46Us4BuR4iH8eIMfqmdg3BzVgpuJ0BWJao/kx3dFWdyA8NbYXfKUqE48SOYes5r00DrZb60FHk5ZqL36XEJD06Jxk46Shlvsk18IhhlR+RW8kQQFJiR9R8ttPbjpzEj4JjAt+ttj9sDgqAoNFldiJyclSJGYeGNh7qmRRCPxkh6HmDlXdKfPE9qCxSPGkAbHFJ1xccKXlJT6Q0PIuIQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.freedesktop.org smtp.mailfrom=amd.com; dmarc=permerror action=none header.from=amd.com; dkim=none (message not signed); arc=none Received: from BN6PR12CA0037.namprd12.prod.outlook.com (2603:10b6:405:70::23) by CY4PR12MB1190.namprd12.prod.outlook.com (2603:10b6:903:39::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2387.22; Tue, 29 Oct 2019 13:52:52 +0000 Received: from CO1NAM03FT048.eop-NAM03.prod.protection.outlook.com (2a01:111:f400:7e48::206) by BN6PR12CA0037.outlook.office365.com (2603:10b6:405:70::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2408.17 via Frontend Transport; Tue, 29 Oct 2019 13:52:51 +0000 Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXMB01.amd.com (165.204.84.17) by CO1NAM03FT048.mail.protection.outlook.com (10.152.81.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2387.20 via Frontend Transport; Tue, 29 Oct 2019 13:52:51 +0000 Received: from SATLEXMB05.amd.com (10.181.40.146) by SATLEXMB01.amd.com (10.181.40.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 29 Oct 2019 08:52:50 -0500 Received: from SATLEXMB01.amd.com (10.181.40.142) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 29 Oct 2019 08:52:50 -0500 Received: from mlipski-pc.amd.com (10.180.168.240) by SATLEXMB01.amd.com (10.181.40.142) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Tue, 29 Oct 2019 08:52:49 -0500 From: To: Subject: [PATCH 01/13] drm/amd/display: Add MST atomic routines Date: Tue, 29 Oct 2019 09:52:33 -0400 Message-ID: <20191029135245.31152-2-mikita.lipski@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191029135245.31152-1-mikita.lipski@amd.com> References: <20191029135245.31152-1-mikita.lipski@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(346002)(39860400002)(376002)(396003)(136003)(428003)(189003)(199004)(186003)(50226002)(4326008)(305945005)(50466002)(54906003)(53416004)(8936002)(48376002)(76176011)(51416003)(7696005)(478600001)(8676002)(81156014)(81166006)(26005)(2351001)(36756003)(6916009)(16586007)(126002)(486006)(446003)(11346002)(2616005)(476003)(336012)(426003)(316002)(14444005)(47776003)(2906002)(356004)(6666004)(1076003)(5660300002)(70586007)(2876002)(86362001)(70206006)(16060500001); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR12MB1190; H:SATLEXMB01.amd.com; FPR:; SPF:None; LANG:en; PTR:InfoDomainNonexistent; MX:1; A:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 240e47f9-b0cb-437b-ccc8-08d75c774a67 X-MS-TrafficTypeDiagnostic: CY4PR12MB1190: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:265; X-Forefront-PRVS: 0205EDCD76 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZS92ShYOW5CkehrBgp1u/J+UzgQH0ziGzR+Frw4/ptAM5kaNhp8xYYrgKT6u9OK5KO6nTsm5yfmw6KOyjkk5XRjym+YPhqbo9tChMdP4dG6rseang5C8JQQtl6Hi125ipBS6pgNn6yYDlmvPZ1hf2ujmRrsi3poDRdMMNIKo55kBnLfNIwojrhtl99EkcoL4h7+/n25caTzfyKXt9WpjjhPLv1aLgSlJ4U142FEyHnHT7gbjPEuhnDxNM8c9qo03oHk/jW0T0hiK1dLnpi+NGpENyGXhMPKIi0iDMPGNmB/SllVhaHBmLCQb/6AaZUwxy5WiwJ0o9zQeb/kCwBSwVjEoytZ61WjwGXXeYI3upp/mDw0izWmHERjxyLYThgKpyZCT+k8fQx1sSGyWNVGNKDCYm8srDBZCt9KZSBlIW8q1dyj62AZQl4x4djacIg1z X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2019 13:52:51.3773 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 240e47f9-b0cb-437b-ccc8-08d75c774a67 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1190 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jUXd+gNjqKSXAZLjxfZe6ovy4XKjOhe5JAT5Rspt6h0=; b=gF4DHhrnTP3Djd5W9J/lmiO2KqDnw147qJLMb6QjXrSupaThuUkkGFDx4OrxHY+LOoZRIu3fUufpgiMD6HhrueCpeo2tbt7cjG/AIAtYqnKg8NGbAenNBesYOiXOXo42MkYCNxAF2ukTdZ/p5hqA6tFo/wedaLCN618DeZzSB3k= X-Mailman-Original-Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jun Lei , dri-devel@lists.freedesktop.org, Jerry Zuo , Mikita Lipski , Nicholas Kazlauskas Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Mikita Lipski - Adding encoder atomic check to find vcpi slots for a connector - Using DRM helper functions to calculate PBN - Adding connector atomic check to release vcpi slots if connector loses CRTC - Calculate PBN and VCPI slots only once during atomic check and store them on crtc_state to eliminate redundant calculation - Call drm_dp_mst_atomic_check to verify validity of MST topology during state atomic check v2: squashed previous 3 separate patches, removed DSC PBN calculation, and added PBN and VCPI slots properties to amdgpu connector v3: - moved vcpi_slots and pbn properties to dm_crtc_state and dc_stream_state - updates stream's vcpi_slots and pbn on commit - separated patch from the DSC MST series v4: - set vcpi_slots and pbn properties to dm_connector_state - copy porperties from connector state on to crtc state v5: - keep the pbn and vcpi values only on connnector state - added a void pointer to the stream state instead on two ints, because dc_stream_state is OS agnostic. Pointer points to the current dm_connector_state. v6: - Remove new param from stream Cc: Jun Lei Cc: Jerry Zuo Cc: Harry Wentland Cc: Nicholas Kazlauskas Cc: Lyude Paul Signed-off-by: Mikita Lipski --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++++++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 + .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 51 +++++-------------- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 32 ++++++++++++ 4 files changed, 86 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 48f5b43e2698..28f6b93ab371 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4180,7 +4180,8 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) state->underscan_hborder = 0; state->underscan_vborder = 0; state->base.max_requested_bpc = 8; - + state->vcpi_slots = 0; + state->pbn = 0; if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) state->abm_level = amdgpu_dm_abm_level; @@ -4209,7 +4210,8 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) new_state->underscan_enable = state->underscan_enable; new_state->underscan_hborder = state->underscan_hborder; new_state->underscan_vborder = state->underscan_vborder; - + new_state->vcpi_slots = state->vcpi_slots; + new_state->pbn = state->pbn; return &new_state->base; } @@ -4610,6 +4612,37 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct drm_atomic_state *state = crtc_state->state; + struct drm_connector *connector = conn_state->connector; + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state); + const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; + struct drm_dp_mst_topology_mgr *mst_mgr; + struct drm_dp_mst_port *mst_port; + int clock, bpp = 0; + + if (!aconnector->port || !aconnector->dc_sink) + return 0; + + mst_port = aconnector->port; + mst_mgr = &aconnector->mst_port->mst_mgr; + + if (!crtc_state->connectors_changed && !crtc_state->mode_changed) + return 0; + + if (!state->duplicated) { + bpp = (uint8_t)connector->display_info.bpc * 3; + clock = adjusted_mode->clock; + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp); + } + dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, + mst_mgr, + mst_port, + dm_new_connector_state->pbn); + if (dm_new_connector_state->vcpi_slots < 0) { + DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", dm_new_connector_state->vcpi_slots); + return dm_new_connector_state->vcpi_slots; + } return 0; } @@ -7651,6 +7684,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; + /* Perform validation of MST topology in the state*/ + ret = drm_dp_mst_atomic_check(state); + if (ret) + goto fail; + if (state->legacy_cursor_update) { /* * This is a fast cursor update coming from the plane update diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index c6fdebee7189..910c8598faf9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -360,6 +360,8 @@ struct dm_connector_state { bool freesync_enable; bool freesync_capable; uint8_t abm_level; + uint64_t vcpi_slots; + uint64_t pbn; }; #define to_dm_connector_state(x)\ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 11e5784aa62a..1b2cc85b4815 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -182,15 +182,20 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( bool enable) { struct amdgpu_dm_connector *aconnector; + struct drm_connector *connector; + struct dm_connector_state *dm_conn_state; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; - int slots = 0; bool ret; - int clock; - int bpp = 0; - int pbn = 0; aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + /* Accessing the connector state is required for vcpi_slots allocation + * and directly relies on behaviour in commit check + * that blocks before commit guaranteeing that the state + * is not gonna be swapped while still in use in commit tail */ + + dm_conn_state = to_dm_connector_state(aconnector->base.state); + if (!aconnector || !aconnector->mst_port) return false; @@ -203,42 +208,10 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->port; if (enable) { - clock = stream->timing.pix_clk_100hz / 10; - - switch (stream->timing.display_color_depth) { - - case COLOR_DEPTH_666: - bpp = 6; - break; - case COLOR_DEPTH_888: - bpp = 8; - break; - case COLOR_DEPTH_101010: - bpp = 10; - break; - case COLOR_DEPTH_121212: - bpp = 12; - break; - case COLOR_DEPTH_141414: - bpp = 14; - break; - case COLOR_DEPTH_161616: - bpp = 16; - break; - default: - ASSERT(bpp != 0); - break; - } - - bpp = bpp * 3; - - /* TODO need to know link rate */ - - pbn = drm_dp_calc_pbn_mode(clock, bpp); - - slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); - ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots); + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, + dm_conn_state->pbn, + dm_conn_state->vcpi_slots); if (!ret) return false; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 779d0b60cac9..1a17ea1b42e0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -251,10 +251,42 @@ dm_mst_atomic_best_encoder(struct drm_connector *connector, return &to_amdgpu_dm_connector(connector)->mst_encoder->base; } +static int dm_dp_mst_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct drm_connector_state *new_conn_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_conn_state = + drm_atomic_get_old_connector_state(state, connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct drm_crtc_state *new_crtc_state; + struct drm_dp_mst_topology_mgr *mst_mgr; + struct drm_dp_mst_port *mst_port; + + mst_port = aconnector->port; + mst_mgr = &aconnector->mst_port->mst_mgr; + + if (!old_conn_state->crtc) + return 0; + + if (new_conn_state->crtc) { + new_crtc_state = drm_atomic_get_old_crtc_state(state, new_conn_state->crtc); + if (!new_crtc_state || + !drm_atomic_crtc_needs_modeset(new_crtc_state) || + new_crtc_state->enable) + return 0; + } + + return drm_dp_atomic_release_vcpi_slots(state, + mst_mgr, + mst_port); +} + static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { .get_modes = dm_dp_mst_get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_best_encoder = dm_mst_atomic_best_encoder, + .atomic_check = dm_dp_mst_atomic_check, }; static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)