From patchwork Wed Nov 6 16:58:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 11230747 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C375A1575 for ; Wed, 6 Nov 2019 17:01:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id ABF0B222C9 for ; Wed, 6 Nov 2019 17:01:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ABF0B222C9 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gerhold.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 38F826E277; Wed, 6 Nov 2019 17:01:14 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mo6-p02-ob.smtp.rzone.de (mo6-p02-ob.smtp.rzone.de [IPv6:2a01:238:20a:202:5302::3]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B42D6E277 for ; Wed, 6 Nov 2019 17:01:09 +0000 (UTC) X-RZG-AUTH: ":P3gBZUipdd93FF5ZZvYFPugejmSTVR2nRPhVORvLd4SsytBXQrEOHTIXs8PvtBNfIQ==" X-RZG-CLASS-ID: mo00 Received: from localhost.localdomain by smtp.strato.de (RZmta 44.29.0 AUTH) with ESMTPSA id e07688vA6H14hLu (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Wed, 6 Nov 2019 18:01:04 +0100 (CET) From: Stephan Gerhold To: Linus Walleij Subject: [PATCH 4/7] drm/mcde: dsi: Delay start of video stream generator Date: Wed, 6 Nov 2019 17:58:32 +0100 Message-Id: <20191106165835.2863-5-stephan@gerhold.net> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106165835.2863-1-stephan@gerhold.net> References: <20191106165835.2863-1-stephan@gerhold.net> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1573059668; s=strato-dkim-0002; d=gerhold.net; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=TU8xWeq3Fq2kfoIu2yX7EJClpaSQfLxdKJkoXF7JaIQ=; b=pyMOfJPYoU+oB9gSN57jQK09wpZ632KRh1qsA7YFz6u2j4xYIbCNuiptAlkxpBSILU gdW5RoooG0i18Vx0rFSIpIHZci9KUwninov2fFrRH3yP21kSjQDzCcIc8aUcTqwkW45X qWUL0wnKCkAfqfKin15pwi+fcHyvTbM71rflpnXDbKP4BF0+zc5gEO1lUZXksi9mL1Jh F4LsR5szBZgTlWRngbE2kyOqNaxWkzHPDeHV9UKKT0Sv8DVM4QxicMr4w2qqcOVczm5g rn5kWZBPIY3Au2o/qoKRjwKqmWcvweLMH32SZIgbHXN8mul0WqJl5NwB6U+UNAIdg9Wz nSZQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Stephan Gerhold , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The initialization order for DSI video mode is important - if we enable the video stream generator (VSG) before the MCDE DSI formatter starts sending pixel data, it will immediately run into an error and disable itself again. Avoid this problem by delaying the activation of the VSG until the MCDE DSI formatter is properly set up and running (i.e. when mcde_dsi_bridge_enable() is called). Signed-off-by: Stephan Gerhold --- drivers/gpu/drm/mcde/mcde_dsi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mcde/mcde_dsi.c b/drivers/gpu/drm/mcde/mcde_dsi.c index c7956c92b51b..4710f23b2966 100644 --- a/drivers/gpu/drm/mcde/mcde_dsi.c +++ b/drivers/gpu/drm/mcde/mcde_dsi.c @@ -583,11 +583,6 @@ static void mcde_dsi_setup_video_mode(struct mcde_dsi *d, val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC; val |= DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA; writel(val, d->regs + DSI_VID_MODE_STS_CTL); - - /* Enable video mode */ - val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); - val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; - writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); } static void mcde_dsi_start(struct mcde_dsi *d) @@ -699,6 +694,14 @@ static void mcde_dsi_start(struct mcde_dsi *d) static void mcde_dsi_bridge_enable(struct drm_bridge *bridge) { struct mcde_dsi *d = bridge_to_mcde_dsi(bridge); + u32 val; + + if (d->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + /* Enable video mode */ + val = readl(d->regs + DSI_MCTL_MAIN_DATA_CTL); + val |= DSI_MCTL_MAIN_DATA_CTL_VID_EN; + writel(val, d->regs + DSI_MCTL_MAIN_DATA_CTL); + } dev_info(d->dev, "enable DSI master\n"); };