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[79.139.233.37]) by smtp.gmail.com with ESMTPSA id j23sm9166942lji.41.2019.11.18.12.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 12:05:44 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Mikko Perttunen , Georgi Djakov , Rob Herring Subject: [PATCH v1 14/29] memory: tegra: Add interconnect nodes for Terga20 display controllers Date: Mon, 18 Nov 2019 23:02:32 +0300 Message-Id: <20191118200247.3567-15-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118200247.3567-1-digetx@gmail.com> References: <20191118200247.3567-1-digetx@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 19 Nov 2019 08:04:07 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AXPcCtWfFdM922/tpHZwDdON4BCmhCdgkfo59YRa3Do=; b=UDlBXSLm5h/lMmeVtYLejQYPHEsYXSZt3oTVz+XKp/fNbo2O4nKCfW2bZI+3IuE+Gc yxvWBMUJf7quIzxKH7PshGVB2yp/jpvVCAEo+oA5/fqQEGpMhGrdlilCm57lbhZ5PDlY rc4StURSae5b2aJ5GwKgb013v8JxYtmHfpPA/no7u7nAVOXjPy/5Xo+shDxKMqfACN7s lD73XIPwL9JmMQM4po8XQTZtfZjGZs6GZzctIJ6eh+F80BzBBXnNxG5VQxtf4BeUIsUi GeZbEtNxNayWO0hIs7l9uAdXC0IyNHLECm8ZtfjpUZpEf5ZGCk4btLlg2MlJed9wZYd0 rU5Q== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add initial interconnect nodes that allow display controller driver to perform memory bandwidth requests using interconnect API. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra/tegra20.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a8098bff91d9..dfcd9fdb7ce7 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -3,6 +3,7 @@ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ +#include #include #include "mc.h" @@ -280,6 +281,17 @@ static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { .reset_status = tegra20_mc_reset_status, }; +#define TEGRA20_MC_ICC(_name) \ + { \ + .name = #_name, \ + .id = TEGRA_ICC_MC_##_name, \ + } + +static const struct tegra_mc_icc_node tegra20_mc_icc_nodes[] = { + TEGRA20_MC_ICC(DC), + TEGRA20_MC_ICC(DCB), +}; + const struct tegra_mc_soc tegra20_mc_soc = { .clients = tegra20_mc_clients, .num_clients = ARRAY_SIZE(tegra20_mc_clients), @@ -290,4 +302,6 @@ const struct tegra_mc_soc tegra20_mc_soc = { .reset_ops = &tegra20_mc_reset_ops, .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), + .icc_nodes = tegra20_mc_icc_nodes, + .num_icc_nodes = ARRAY_SIZE(tegra20_mc_icc_nodes), };