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[79.139.233.37]) by smtp.gmail.com with ESMTPSA id j23sm9166942lji.41.2019.11.18.12.05.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Nov 2019 12:05:36 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Mikko Perttunen , Georgi Djakov , Rob Herring Subject: [PATCH v1 07/29] dt-bindings: host1x: Document new interconnect properties Date: Mon, 18 Nov 2019 23:02:25 +0300 Message-Id: <20191118200247.3567-8-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191118200247.3567-1-digetx@gmail.com> References: <20191118200247.3567-1-digetx@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Tue, 19 Nov 2019 08:04:07 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bqBrfnW6oyEXwKIsbHDBGjswWgQFyUFjpg74MBWJm98=; b=Z6Kd/3tqBvD0M7O+PYu7Ii8RlXO0+YawGtX5h9TllVokV9Qzmc+mmaZJjKwaOqN20S vciRZM10CNRGSAjggOApBG/aktZ1egddBzZLK1Cw5zVSHj9sY6wnwyqW5LhTDMgVnPO0 kPyiJ1cDdIflcboywIBKSfX4ePvjrzwa7nG11rEtpQ5D6KgvVtOoEz6VJlcVfVKNeSlI BIb+CyR7SSmV/FgJEm+y6wDNdlASp9ZOb45u3YD6ox8labjdDyVAwSbgp/tDlgQqZbvC bdvpkMWX6vR8WxszZg37yPD/36pBzeVdUMd5TohZlebNd0V9EJJsTU0dYC/4aGI3RELa kAyQ== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pm@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Host1x clients are interconnected with memory controller through Graphics HOST bus, these clients will issue memory bandwidth requests to the memory controller that will adapt arbitration configuration in order to satisfy clients and then propagate the aggregated bandwidth request to external memory controller. The new interconnect properties are optional, thus backwards compatibility is preserved with older device-trees. Signed-off-by: Dmitry Osipenko --- .../display/tegra/nvidia,tegra20-host1x.txt | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index 9999255ac5b6..2a1fc1a194d2 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,11 @@ Required properties: - reset-names: Must include the following entries: - host1x +Each host1x client module having to perform DMA through the Memory Controller +should have the interconnect endpoints set to the Memory Client and External +Memory respectively, interconnect name must be set to "dma-mem". +The interconnect property is optional. + The host1x top-level node defines a number of children, each representing one of the following host1x client modules: @@ -36,6 +41,11 @@ of the following host1x client modules: - reset-names: Must include the following entries: - mpe + Optional properties: + - interconnects: Must contain entry for the memory interconnect. + - interconnect-names: Must include the following entries: + - dma-mem + - vi: video input Required properties: @@ -49,6 +59,11 @@ of the following host1x client modules: - reset-names: Must include the following entries: - vi + Optional properties: + - interconnects: Must contain entry for the memory interconnect. + - interconnect-names: Must include the following entries: + - dma-mem + - epp: encoder pre-processor Required properties: @@ -62,6 +77,11 @@ of the following host1x client modules: - reset-names: Must include the following entries: - epp + Optional properties: + - interconnects: Must contain entry for the memory interconnect. + - interconnect-names: Must include the following entries: + - dma-mem + - isp: image signal processor Required properties: @@ -75,6 +95,11 @@ of the following host1x client modules: - reset-names: Must include the following entries: - isp + Optional properties: + - interconnects: Must contain entry for the memory interconnect. + - interconnect-names: Must include the following entries: + - dma-mem + - gr2d: 2D graphics engine Required properties: @@ -88,6 +113,11 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 2d + Optional properties: + - interconnects: Must contain entry for the memory interconnect. + - interconnect-names: Must include the following entries: + - dma-mem + - gr3d: 3D graphics engine Required properties: @@ -106,6 +136,11 @@ of the following host1x client modules: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + Optional properties: + - interconnects: Must contain entry for the memory interconnect. + - interconnect-names: Must include the following entries: + - dma-mem + - dc: display controller Required properties: @@ -133,6 +168,9 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - interconnects: Must contain entry for the memory interconnect. + - interconnect-names: Must include the following entries: + - dma-mem - hdmi: High Definition Multimedia Interface @@ -281,6 +319,11 @@ of the following host1x client modules: - reset-names: Must include the following entries: - vic + Optional properties: + - interconnects: Must contain entry for the memory interconnect. + - interconnect-names: Must include the following entries: + - dma-mem + Example: / { @@ -307,6 +350,9 @@ Example: clocks = <&tegra_car TEGRA20_CLK_MPE>; resets = <&tegra_car 60>; reset-names = "mpe"; + + interconnects = <&mc TEGRA_ICC_MC_MPE &emc TEGRA_ICC_EMEM>; + interconnect-names = "dma-mem"; }; vi { @@ -316,6 +362,9 @@ Example: clocks = <&tegra_car TEGRA20_CLK_VI>; resets = <&tegra_car 100>; reset-names = "vi"; + + interconnects = <&mc TEGRA_ICC_MC_VI &emc TEGRA_ICC_EMEM>; + interconnect-names = "dma-mem"; }; epp { @@ -325,6 +374,9 @@ Example: clocks = <&tegra_car TEGRA20_CLK_EPP>; resets = <&tegra_car 19>; reset-names = "epp"; + + interconnects = <&mc TEGRA_ICC_MC_EPP &emc TEGRA_ICC_EMEM>; + interconnect-names = "dma-mem"; }; isp { @@ -334,6 +386,9 @@ Example: clocks = <&tegra_car TEGRA20_CLK_ISP>; resets = <&tegra_car 23>; reset-names = "isp"; + + interconnects = <&mc TEGRA_ICC_MC_ISP &emc TEGRA_ICC_EMEM>; + interconnect-names = "dma-mem"; }; gr2d { @@ -343,6 +398,9 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR2D>; resets = <&tegra_car 21>; reset-names = "2d"; + + interconnects = <&mc TEGRA_ICC_MC_2D &emc TEGRA_ICC_EMEM>; + interconnect-names = "dma-mem"; }; gr3d { @@ -351,6 +409,9 @@ Example: clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&tegra_car 24>; reset-names = "3d"; + + interconnects = <&mc TEGRA_ICC_MC_3D &emc TEGRA_ICC_EMEM>; + interconnect-names = "dma-mem"; }; dc@54200000 { @@ -363,6 +424,9 @@ Example: resets = <&tegra_car 27>; reset-names = "dc"; + interconnects = <&mc TEGRA_ICC_MC_DC &emc TEGRA_ICC_EMEM>; + interconnect-names = "dma-mem"; + rgb { status = "disabled"; }; @@ -378,6 +442,9 @@ Example: resets = <&tegra_car 26>; reset-names = "dc"; + interconnects = <&mc TEGRA_ICC_MC_DCB &emc TEGRA_ICC_EMEM>; + interconnect-names = "dma-mem"; + rgb { status = "disabled"; };