| Message ID | 20191218143416.v3.4.If3e2d0493e7b6e8b510ea90d8724ff760379b3ba@changeid (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP | expand |
On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote: > The driver used to say that the value to program into bridge register > 0x93 was dp_lanes - 1. Looking at the datasheet for the bridge, this > is wrong. The data sheet says: > * 1 = 1 lane > * 2 = 2 lanes > * 3 = 4 lanes > > A more proper way to express this encoding is min(dp_lanes, 3). > > At the moment this change has zero effect because we've hardcoded the > number of DP lanes to 4. ...and (4 - 1) == min(4, 3). How fortunate! > ...but soon we'll stop hardcoding the number of lanes. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Tested-by: Rob Clark <robdclark@gmail.com> > Reviewed-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > > Changes in v3: None > Changes in v2: None > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index ab644baaf90c..d55d19759796 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -523,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) > CHA_DSI_LANES_MASK, val); > > /* DP lane config */ > - val = DP_NUM_LANES(pdata->dp_lanes - 1); > + val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); > regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, > val); > > -- > 2.24.1.735.g03f4e72817-goog >
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index ab644baaf90c..d55d19759796 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -523,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge) CHA_DSI_LANES_MASK, val); /* DP lane config */ - val = DP_NUM_LANES(pdata->dp_lanes - 1); + val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, val);