| Message ID | 20200213120203.29368-3-nirmoy.das@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | do not store GPU address in TTM | expand |
Am 13.02.20 um 14:28 schrieb Nirmoy: > > On 2/13/20 2:00 PM, Christian König wrote: >> Am 13.02.20 um 13:31 schrieb Nirmoy: >>> >>> On 2/13/20 1:18 PM, Christian König wrote: >>>> Looks like most of the patch is missing? >>>> >>>> We should have quite a number of uses of the BO offset in radeon or >>>> do all of those go through radeon_bo_gpu_offset? >>> Compilation worked so I think all those(bo->offset) accesses went >>> through radeon_bo_gpu_offset. >> >> Cool, than that is a lot easier to implement than I thought it would be. >> >> I assume you don't have Radeon hardware lying around to test this? >> >> If you can you give me a branch on the AMD (or public) servers I can >> give it at least a quick round of testing. > > huh it seems I have to rebase it a bit for drm/drm-next as it is based > on our internal branch :/ > > You can access the branch at > http://gitlab1.amd.com/nirmodas/linux/tree/ttm_clean.1 > > I will rebase this for drm-next in next version of the patch series. Actually you should probably base it on drm-misc-next instead. And additional to the already noted VRAM helpers the bochs driver fails to compile on your branch. The good news is that my old HD5670 still works with the radeon patch applied. So this patch is Reviewed-and-tested-by: Christian König <christian.koenig@amd.com>. Regards, Christian. > >> >> Christian. >> >>>> >>>> If yes then the change is much smaller than I thought i needs to be. >>>> >>>> Christian. >>>> >>> Regards, >>> >>> Nirmoy >>> >>> _______________________________________________ >>> amd-gfx mailing list >>> amd-gfx@lists.freedesktop.org >>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CNirmoy.Das%40amd.com%7C60aa17c05a2f474663f008d7b084b550%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637171956342728389&sdata=I2n0yMXK5CtrG5tY9Q47igxJv9Onb%2FA7PBeLwrpPb54%3D&reserved=0 >>> >>
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index d59b004f6695..97cfcc2870af 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -2823,6 +2823,7 @@ extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size extern void radeon_program_register_sequence(struct radeon_device *rdev, const u32 *registers, const u32 array_size); +struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev); /* * vm diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h index d23f2ed4126e..4d37571c7ff5 100644 --- a/drivers/gpu/drm/radeon/radeon_object.h +++ b/drivers/gpu/drm/radeon/radeon_object.h @@ -90,7 +90,21 @@ static inline void radeon_bo_unreserve(struct radeon_bo *bo) */ static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo) { - return bo->tbo.offset; + struct radeon_device *rdev; + u64 start = 0; + + rdev = radeon_get_rdev(bo->tbo.bdev); + + switch(bo->tbo.mem.mem_type) { + case TTM_PL_TT: + start = rdev->mc.gtt_start; + break; + case TTM_PL_VRAM: + start = rdev->mc.vram_start; + break; + } + + return (bo->tbo.mem.start << PAGE_SHIFT) + start; } static inline unsigned long radeon_bo_size(struct radeon_bo *bo) diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 098bc9f40b98..b10654494262 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -56,7 +56,7 @@ static int radeon_ttm_debugfs_init(struct radeon_device *rdev); static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); -static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) +struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) { struct radeon_mman *mman; struct radeon_device *rdev; @@ -87,7 +87,6 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, break; case TTM_PL_TT: man->func = &ttm_bo_manager_func; - man->gpu_offset = rdev->mc.gtt_start; man->available_caching = TTM_PL_MASK_CACHING; man->default_caching = TTM_PL_FLAG_CACHED; man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; @@ -109,7 +108,6 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, case TTM_PL_VRAM: /* "On-card" video ram */ man->func = &ttm_bo_manager_func; - man->gpu_offset = rdev->mc.vram_start; man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_MAPPABLE; man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> --- drivers/gpu/drm/radeon/radeon.h | 1 + drivers/gpu/drm/radeon/radeon_object.h | 16 +++++++++++++++- drivers/gpu/drm/radeon/radeon_ttm.c | 4 +--- 3 files changed, 17 insertions(+), 4 deletions(-)