Message ID | 20200302203452.17977-2-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/panel: Fix dotclocks | expand |
Hi Ville, On Mon, Mar 2, 2020 at 9:34 PM Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > .mode = { > /* The internal pixel clock of the NT35510 is 20 MHz */ > - .clock = 20000000, > + .clock = 23581, I double checked this with the datasheet NT35510 Application Note V0.07 HYDIS and all documentation is in line with the comment: the internal clock frequency of the dotclock is 20 MHz so this should be set to 20000 (kHz) sorry for putting the three orders of magnitude too big number there :P This clock isn't used by any drivers because this is a command mode DSI panel with a DSI link clocked from the host. (hs_rate or lp_rate). The internal formula shows how the actual vrefresh can be calculated for the display in respone to setting of the internal registers, see page 34: https://dflund.se/~triad/NT35510-appnote.pdf Yours, Linus Walleij
diff --git a/drivers/gpu/drm/panel/panel-novatek-nt35510.c b/drivers/gpu/drm/panel/panel-novatek-nt35510.c index b4c014126781..94e294b66a6a 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt35510.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt35510.c @@ -1019,7 +1019,7 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = { */ .mode = { /* The internal pixel clock of the NT35510 is 20 MHz */ - .clock = 20000000, + .clock = 23581, .hdisplay = 480, .hsync_start = 480 + 2, /* HFP = 2 */ .hsync_end = 480 + 2 + 0, /* HSync = 0 */