From patchwork Wed Mar 18 06:35:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11444627 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 776BB1392 for ; Wed, 18 Mar 2020 06:34:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5FE9C2076F for ; Wed, 18 Mar 2020 06:34:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5FE9C2076F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BE556E86F; Wed, 18 Mar 2020 06:33:51 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 19E73898CE; Wed, 18 Mar 2020 06:33:48 +0000 (UTC) IronPort-SDR: SqEtN9/E8/jwY5V6hDAm8C38ojeIGQs13sBDFfaQwpDVhR19b72Lq2wokCM9mHJk+1at59o0HH 2qJ4aMPYKTkw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Mar 2020 23:33:47 -0700 IronPort-SDR: KTi2+Je3Z5QzX1f/QuXhoYMQ8zsv8fJDoFimqj/t6cxH+/YXXIymzMGiS/xzT1UNXCiGCbik1u RwJI7wF0Dviw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,566,1574150400"; d="scan'208";a="417839761" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga005.jf.intel.com with ESMTP; 17 Mar 2020 23:33:47 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH 3/3] drm/i915/dp: intel_dp connector hook for VRR support Date: Tue, 17 Mar 2020 23:35:17 -0700 Message-Id: <20200318063517.3844-3-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20200318063517.3844-1-manasi.d.navare@intel.com> References: <20200318063517.3844-1-manasi.d.navare@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aditya Swarup , Manasi Navare , Nicholas Kazlauskas Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This defines the get_vrr_support hook for intel DP connector VRR support is set to true based on the DPCD ignore MSA and EDID monitor range Cc: Jani Nikula Cc: Ville Syrjälä Cc: Harry Wentland Cc: Nicholas Kazlauskas Cc: Aditya Swarup Signed-off-by: Manasi Navare --- .../drm/i915/display/intel_display_types.h | 3 +++ drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 5e00e611f077..cd37ee6db1ff 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1353,6 +1353,9 @@ struct intel_dp { /* Display stream compression testing */ bool force_dsc_en; + + /* DP Variable refresh rate/ Adaptive sync support */ + bool vrr_capable; }; enum lspcon_vendor { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0a417cd2af2b..ccf5d868b5c1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5860,6 +5860,24 @@ static int intel_dp_get_modes(struct drm_connector *connector) return 0; } +static void intel_dp_get_vrr_support(struct drm_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + if (INTEL_GEN(dev_priv) >= 12 && + drm_dp_sink_is_capable_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10) + intel_dp->vrr_capable = true; +} + static int intel_dp_connector_register(struct drm_connector *connector) { @@ -6756,6 +6774,7 @@ static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = .get_modes = intel_dp_get_modes, .mode_valid = intel_dp_mode_valid, .atomic_check = intel_dp_connector_atomic_check, + .get_adaptive_sync_support = intel_dp_get_vrr_support, }; static const struct drm_encoder_funcs intel_dp_enc_funcs = {