diff mbox series

[2/3] gpu/drm: Fix spelling of *frequency*

Message ID 20200510120835.32054-2-pmenzel@molgen.mpg.de (mailing list archive)
State New, archived
Headers show
Series [1/3] gpu/drm: Fix spelling of *sequence* and *frequency* | expand

Commit Message

Paul Menzel May 10, 2020, 12:08 p.m. UTC 
Fix all occurrences with the command below.

    git grep -l frequencey | xargs sed -i 's/frequencey/frequency/g'

Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: David (ChunMing) Zhou <David1.Zhou@amd.com>
Cc: amd-gfx@lists.freedesktop.org
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
---
 drivers/gpu/drm/amd/include/atombios.h | 4 ++--
 drivers/gpu/drm/msm/dsi/dsi_host.c     | 2 +-
 drivers/gpu/drm/radeon/atombios.h      | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h
index afef574c3b88b..7fe1d0d66701c 100644
--- a/drivers/gpu/drm/amd/include/atombios.h
+++ b/drivers/gpu/drm/amd/include/atombios.h
@@ -6138,7 +6138,7 @@  ucLVDSOffToOnDelay_in4Ms:         LVDS power down sequence time in unit of 4ms.
 
 ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
 
-ulNbpStateMemclkFreq[4]:          system memory clock frequencey in unit of 10Khz in different NB pstate.
+ulNbpStateMemclkFreq[4]:          system memory clock frequency in unit of 10Khz in different NB pstate.
 
 **********************************************************************************************************************/
 
@@ -6346,7 +6346,7 @@  ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is custom
 
 ulLCDBitDepthControlVal:          GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
 
-ulNbpStateMemclkFreq[4]:          system memory clock frequencey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
+ulNbpStateMemclkFreq[4]:          system memory clock frequency in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
 ulNbpStateNClkFreq[4]:            NB P-State NClk frequency in different NB P-State
 usNBPStateVoltage[4]:             NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
 usBootUpNBVoltage:                NB P-State voltage during boot up before driver loaded
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 11ae5b8444c32..7b50c2b7af74f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -743,7 +743,7 @@  int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi)
 	 * esc clock is byte clock followed by a 4 bit divider,
 	 * we need to find an escape clock frequency within the
 	 * mipi DSI spec range within the maximum divider limit
-	 * We iterate here between an escape clock frequencey
+	 * We iterate here between an escape clock frequency
 	 * between 20 Mhz to 5 Mhz and pick up the first one
 	 * that can be supported by our divider
 	 */
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 4d0f6de32957f..b9d7d54e537cf 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -5206,7 +5206,7 @@  ucLVDSOffToOnDelay_in4Ms:         LVDS power down sequence time in unit of 4ms.
 
 ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 
 
-ulNbpStateMemclkFreq[4]:          system memory clock frequencey in unit of 10Khz in different NB pstate. 
+ulNbpStateMemclkFreq[4]:          system memory clock frequency in unit of 10Khz in different NB pstate. 
 
 **********************************************************************************************************************/
 
@@ -5413,7 +5413,7 @@  ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is custom
 
 ulLCDBitDepthControlVal:          GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
 
-ulNbpStateMemclkFreq[4]:          system memory clock frequencey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
+ulNbpStateMemclkFreq[4]:          system memory clock frequency in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
 ulNbpStateNClkFreq[4]:            NB P-State NClk frequency in different NB P-State
 usNBPStateVoltage[4]:             NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
 usBootUpNBVoltage:                NB P-State voltage during boot up before driver loaded