[3/3] gpu/drm/radeon: Remove trailing spaces from ATOMBIOS header file

Message ID	20200510120835.32054-3-pmenzel@molgen.mpg.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=C8n3=6Z=lists.freedesktop.org=dri-devel-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ADBB0208DB From: Paul Menzel <pmenzel@molgen.mpg.de> To: dri-devel@lists.freedesktop.org Subject: [PATCH 3/3] gpu/drm/radeon: Remove trailing spaces from ATOMBIOS header file Date: Sun, 10 May 2020 14:08:35 +0200 Message-Id: <20200510120835.32054-3-pmenzel@molgen.mpg.de> In-Reply-To: <20200510120835.32054-1-pmenzel@molgen.mpg.de> References: <20200510120835.32054-1-pmenzel@molgen.mpg.de> MIME-Version: 1.0 Precedence: list Cc: Alex Deucher <alexander.deucher@amd.com>, Paul Menzel <pmenzel@molgen.mpg.de>, =?utf-8?q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>, amd-gfx@lists.freedesktop.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
Series	[1/3] gpu/drm: Fix spelling of sequence and frequency \| expand [1/3] gpu/drm: Fix spelling of sequence and frequency [2/3] gpu/drm: Fix spelling of frequency [3/3] gpu/drm/radeon: Remove trailing spaces from ATOMBIOS header file

diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index b9d7d54e537cf..110f15fed92e8 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h @@ -1,5 +1,5 @@ /* - * Copyright 2006-2007 Advanced Micro Devices, Inc. + * Copyright 2006-2007 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -21,7 +21,7 @@ */ -/****************************************************************************/ +/****************************************************************************/ /*Portion I: Definitions shared between VBIOS and Driver */ /****************************************************************************/ @@ -42,7 +42,7 @@ #endif #ifdef _H2INC - #ifndef ULONG + #ifndef ULONG typedef unsigned long ULONG; #endif @@ -50,12 +50,12 @@ typedef unsigned char UCHAR; #endif - #ifndef USHORT + #ifndef USHORT typedef unsigned short USHORT; #endif #endif - -#define ATOM_DAC_A 0 + +#define ATOM_DAC_A 0 #define ATOM_DAC_B 1 #define ATOM_EXT_DAC 2 @@ -81,7 +81,7 @@ #define ATOM_EXT_CLOCK 10 #define ATOM_PPLL_INVALID 0xFF -#define ENCODER_REFCLK_SRC_P1PLL 0 +#define ENCODER_REFCLK_SRC_P1PLL 0 #define ENCODER_REFCLK_SRC_P2PLL 1 #define ENCODER_REFCLK_SRC_DCPLL 2 #define ENCODER_REFCLK_SRC_EXTCLK 3 @@ -90,10 +90,10 @@ #define ATOM_SCALER1 0 #define ATOM_SCALER2 1 -#define ATOM_SCALER_DISABLE 0 -#define ATOM_SCALER_CENTER 1 -#define ATOM_SCALER_EXPANSION 2 -#define ATOM_SCALER_MULTI_EX 3 +#define ATOM_SCALER_DISABLE 0 +#define ATOM_SCALER_CENTER 1 +#define ATOM_SCALER_EXPANSION 2 +#define ATOM_SCALER_MULTI_EX 3 #define ATOM_DISABLE 0 #define ATOM_ENABLE 1 @@ -137,7 +137,7 @@ #define ATOM_DAC2_CV ATOM_DAC1_CV #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC #define ATOM_DAC2_PAL ATOM_DAC1_PAL - + #define ATOM_PM_ON 0 #define ATOM_PM_STANDBY 1 #define ATOM_PM_SUSPEND 2 @@ -173,7 +173,7 @@ #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop -#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING +#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) @@ -194,7 +194,7 @@ #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e /* Common header for all ROM Data tables. - Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. + Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. And the pointer actually points to this header. */ typedef struct _ATOM_COMMON_TABLE_HEADER @@ -205,13 +205,13 @@ typedef struct _ATOM_COMMON_TABLE_HEADER /*Image can't be updated, while Driver needs to carry the new table! */ }ATOM_COMMON_TABLE_HEADER; -/****************************************************************************/ +/****************************************************************************/ // Structure stores the ROM header. -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_ROM_HEADER { ATOM_COMMON_TABLE_HEADER sHeader; - UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, + UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, atombios should init it as "ATOM", don't change the position */ USHORT usBiosRuntimeSegmentAddress; USHORT usProtectedModeInfoOffset; @@ -223,7 +223,7 @@ typedef struct _ATOM_ROM_HEADER USHORT usIoBaseAddress; USHORT usSubsystemVendorID; USHORT usSubsystemID; - USHORT usPCI_InfoOffset; + USHORT usPCI_InfoOffset; USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ UCHAR ucExtendedFunctionCode; @@ -237,9 +237,9 @@ typedef struct _ATOM_ROM_HEADER #define USHORT void* #endif -/****************************************************************************/ -// Structures used in Command.mtb -/****************************************************************************/ +/****************************************************************************/ +// Structures used in Command.mtb +/****************************************************************************/ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON @@ -253,50 +253,50 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT GPIOPinControl; //Atomic Table, only used by Bios USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 - USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 + USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT MemoryPLLInit; //Atomic Table, used only by Bios - USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. - USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock + USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. + USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios - USHORT SetUniphyInstance; //Atomic Table, only used by Bios - USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 + USHORT SetUniphyInstance; //Atomic Table, only used by Bios + USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 - USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead + USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead USHORT GetConditionalGoldenSetting; //Only used by Bios USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 USHORT PatchMCSetting; //only used by BIOS USHORT MC_SEQ_Control; //only used by BIOS USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting USHORT EnableScaler; //Atomic Table, used only by Bios - USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 + USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios - USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios USHORT LUT_AutoFill; //Atomic Table, only used by Bios USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios - USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 - USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 + USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios - USHORT MemoryCleanUp; //Atomic Table, only used by Bios + USHORT MemoryCleanUp; //Atomic Table, only used by Bios USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios - USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components + USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 @@ -318,22 +318,22 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 - USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 + USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios USHORT DPEncoderService; //Function Table,only used by Bios USHORT GetVoltageInfo; //Function Table,only used by Bios since SI -}ATOM_MASTER_LIST_OF_COMMAND_TABLES; +}ATOM_MASTER_LIST_OF_COMMAND_TABLES; -// For backward compatible +// For backward compatible #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction #define DPTranslatorControl DIG2EncoderControl #define UNIPHYTransmitterControl DIG1TransmitterControl #define LVTMATransmitterControl DIG2TransmitterControl #define SetCRTC_DPM_State GetConditionalGoldenSetting -#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance +#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance #define HPDInterruptService ReadHWAssistedI2CStatus #define EnableVGA_Access GetSCLKOverMCLKRatio -#define EnableYUV GetDispObjectInfo +#define EnableYUV GetDispObjectInfo #define DynamicClockGating EnableDispPowerGating #define SetupHWAssistedI2CStatus ComputeMemoryClockParam @@ -348,18 +348,18 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; }ATOM_MASTER_COMMAND_TABLE; -/****************************************************************************/ +/****************************************************************************/ // Structures used in every command table -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_TABLE_ATTRIBUTE { #if ATOM_BIG_ENDIAN USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag - USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), - USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), #else - USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), - USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag #endif }ATOM_TABLE_ATTRIBUTE; @@ -370,37 +370,37 @@ typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS USHORT susAccess; }ATOM_TABLE_ATTRIBUTE_ACCESS; -/****************************************************************************/ +/****************************************************************************/ // Common header for all command tables. -// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. +// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. // And the pointer actually points to this header. -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER { ATOM_COMMON_TABLE_HEADER CommonHeader; - ATOM_TABLE_ATTRIBUTE TableAttribute; + ATOM_TABLE_ATTRIBUTE TableAttribute; }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; -/****************************************************************************/ +/****************************************************************************/ // Structures used by ComputeMemoryEnginePLLTable -/****************************************************************************/ +/****************************************************************************/ #define COMPUTE_MEMORY_PLL_PARAM 1 #define COMPUTE_ENGINE_PLL_PARAM 2 #define ADJUST_MC_SETTING_PARAM 3 -/****************************************************************************/ +/****************************************************************************/ // Structures used by AdjustMemoryControllerTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ { #if ATOM_BIG_ENDIAN - ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block + ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] ULONG ulClockFreq:24; #else ULONG ulClockFreq:24; ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] - ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block + ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block #endif }ATOM_ADJUST_MEMORY_CLOCK_FREQ; #define POINTER_RETURN_FLAG 0x80 @@ -408,7 +408,7 @@ typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS { ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div - UCHAR ucAction; //0:reserved //1:Memory //2:Engine + UCHAR ucAction; //0:reserved //1:Memory //2:Engine UCHAR ucReserved; //may expand to return larger Fbdiv later UCHAR ucFbDiv; //return value UCHAR ucPostDiv; //return value @@ -416,7 +416,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 { - ULONG ulClock; //When return, [23:0] return real clock + ULONG ulClock; //When return, [23:0] return real clock UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register USHORT usFbDiv; //return Feedback value to be written to register UCHAR ucPostDiv; //return post div to be written to register @@ -451,8 +451,8 @@ typedef struct _ATOM_COMPUTE_CLOCK_FREQ typedef struct _ATOM_S_MPLL_FB_DIVIDER { - USHORT usFbDivFrac; - USHORT usFbDiv; + USHORT usFbDivFrac; + USHORT usFbDiv; }ATOM_S_MPLL_FB_DIVIDER; typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 @@ -463,9 +463,9 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 ULONG ulClockParams; //ULONG access for BE ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter }; - UCHAR ucRefDiv; //Output Parameter - UCHAR ucPostDiv; //Output Parameter - UCHAR ucCntlFlag; //Output Parameter + UCHAR ucRefDiv; //Output Parameter + UCHAR ucPostDiv; //Output Parameter + UCHAR ucCntlFlag; //Output Parameter UCHAR ucReserved; }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; @@ -481,9 +481,9 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 { #if ATOM_BIG_ENDIAN ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly - ULONG ulClock:24; //Input= target clock, output = actual clock + ULONG ulClock:24; //Input= target clock, output = actual clock #else - ULONG ulClock:24; //Input= target clock, output = actual clock + ULONG ulClock:24; //Input= target clock, output = actual clock ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly #endif }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; @@ -496,14 +496,14 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 ULONG ulClockParams; //ULONG access for BE ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter }; - UCHAR ucRefDiv; //Output Parameter - UCHAR ucPostDiv; //Output Parameter + UCHAR ucRefDiv; //Output Parameter + UCHAR ucPostDiv; //Output Parameter union { UCHAR ucCntlFlag; //Output Flags UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode }; - UCHAR ucReserved; + UCHAR ucReserved; }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; @@ -522,14 +522,14 @@ typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 { COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider - UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider - UCHAR ucPllPostDiv; //Output Parameter: PLL post divider + UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider + UCHAR ucPllPostDiv; //Output Parameter: PLL post divider UCHAR ucPllCntlFlag; //Output Flags: control flag - UCHAR ucReserved; + UCHAR ucReserved; }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; //ucPllCntlFlag -#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 +#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 // ucInputFlag @@ -540,22 +540,22 @@ typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 { union { - ULONG ulClock; + ULONG ulClock; ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) }; - UCHAR ucDllSpeed; //Output + UCHAR ucDllSpeed; //Output UCHAR ucPostDiv; //Output union{ UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode - UCHAR ucPllCntlFlag; //Output: + UCHAR ucPllCntlFlag; //Output: }; - UCHAR ucBWCntl; + UCHAR ucBWCntl; }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; // definition of ucInputFlag #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 // definition of ucPllCntlFlag -#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 +#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 @@ -576,9 +576,9 @@ typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER ULONG ulReserved; }DYNAMICE_ENGINE_SETTINGS_PARAMETER; -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetEngineClockTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_ENGINE_CLOCK_PARAMETERS { ULONG ulTargetEngineClock; //In 10Khz unit @@ -590,9 +590,9 @@ typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; }SET_ENGINE_CLOCK_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetMemoryClockTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_MEMORY_CLOCK_PARAMETERS { ULONG ulTargetMemoryClock; //In 10Khz unit @@ -604,9 +604,9 @@ typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; }SET_MEMORY_CLOCK_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structures used by ASIC_Init.ctb -/****************************************************************************/ +/****************************************************************************/ typedef struct _ASIC_INIT_PARAMETERS { ULONG ulDefaultEngineClock; //In 10Khz unit @@ -619,29 +619,29 @@ typedef struct _ASIC_INIT_PS_ALLOCATION SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure }ASIC_INIT_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structure used by DynamicClockGatingTable.ctb -/****************************************************************************/ -typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS +/****************************************************************************/ +typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE UCHAR ucPadding[3]; }DYNAMIC_CLOCK_GATING_PARAMETERS; #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structure used by EnableDispPowerGatingTable.ctb -/****************************************************************************/ -typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 +/****************************************************************************/ +typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 { UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE UCHAR ucPadding[2]; }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; -/****************************************************************************/ +/****************************************************************************/ // Structure used by EnableASIC_StaticPwrMgtTable.ctb -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE @@ -649,9 +649,9 @@ typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by DAC_LoadDetectionTable.ctb -/****************************************************************************/ +/****************************************************************************/ typedef struct _DAC_LOAD_DETECTION_PARAMETERS { USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} @@ -668,10 +668,10 @@ typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION ULONG Reserved[2];// Don't set this one, allocation for EXT DAC }DAC_LOAD_DETECTION_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb -/****************************************************************************/ -typedef struct _DAC_ENCODER_CONTROL_PARAMETERS +/****************************************************************************/ +typedef struct _DAC_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) @@ -682,28 +682,28 @@ typedef struct _DAC_ENCODER_CONTROL_PARAMETERS #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by DIG1EncoderControlTable // DIG2EncoderControlTable // ExternalEncoderControlTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient - UCHAR ucConfig; + UCHAR ucConfig; // [2] Link Select: // =0: PHY linkA if bfLane<3 // =1: PHY linkB if bfLanes<3 // =0: PHY linkA+B if bfLanes=3 // [3] Transmitter Sel // =0: UNIPHY or PCIEPHY - // =1: LVTMA - UCHAR ucAction; // =0: turn off encoder - // =1: turn on encoder + // =1: LVTMA + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder UCHAR ucLaneNum; // how many lanes to enable @@ -768,11 +768,11 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 { USHORT usPixelClock; // in 10KHz; for bios convenient ATOM_DIG_ENCODER_CONFIG_V2 acConfig; - UCHAR ucAction; + UCHAR ucAction; UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder UCHAR ucLaneNum; // how many lanes to enable @@ -843,12 +843,12 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 { USHORT usPixelClock; // in 10KHz; for bios convenient ATOM_DIG_ENCODER_CONFIG_V3 acConfig; - UCHAR ucAction; + UCHAR ucAction; union { UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder // =5: DP audio @@ -864,7 +864,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 //ucTableFormatRevision=1 //ucTableContentRevision=4 -// start from NI +// start from NI // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 { @@ -902,12 +902,12 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; UCHAR ucConfig; }; - UCHAR ucAction; + UCHAR ucAction; union { UCHAR ucEncoderMode; - // =0: DP encoder - // =1: LVDS encoder - // =2: DVI encoder + // =0: DP encoder + // =1: LVDS encoder + // =2: DVI encoder // =3: HDMI encoder // =4: SDVO encoder // =5: DP audio @@ -921,9 +921,9 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version }DIG_ENCODER_CONTROL_PARAMETERS_V4; -// define ucBitPerColor: +// define ucBitPerColor: #define PANEL_BPC_UNDEFINE 0x00 -#define PANEL_6BIT_PER_COLOR 0x01 +#define PANEL_6BIT_PER_COLOR 0x01 #define PANEL_8BIT_PER_COLOR 0x02 #define PANEL_10BIT_PER_COLOR 0x03 #define PANEL_12BIT_PER_COLOR 0x04 @@ -934,11 +934,11 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 -/****************************************************************************/ +/****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable // LVTMATransmitterControlTable // DVOOutputControlTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_DP_VS_MODE { UCHAR ucLaneSel; @@ -954,36 +954,36 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS ATOM_DP_VS_MODE asMode; // DP Voltage swing mode }; UCHAR ucConfig; - // [0]=0: 4 lane Link, - // =1: 8 lane Link ( Dual Links TMDS ) - // [1]=0: InCoherent mode - // =1: Coherent Mode + // [0]=0: 4 lane Link, + // =1: 8 lane Link ( Dual Links TMDS ) + // [1]=0: InCoherent mode + // =1: Coherent Mode // [2] Link Select: // =0: PHY linkA if bfLane<3 // =1: PHY linkB if bfLanes<3 - // =0: PHY linkA+B if bfLanes=3 + // =0: PHY linkA+B if bfLanes=3 // [5:4]PCIE lane Sel // =0: lane 0~3 or 0~7 // =1: lane 4~7 // =2: lane 8~11 or 8~15 - // =3: lane 12~15 - UCHAR ucAction; // =0: turn off encoder - // =1: turn on encoder + // =3: lane 12~15 + UCHAR ucAction; // =0: turn off encoder + // =1: turn on encoder UCHAR ucReserved[4]; }DIG_TRANSMITTER_CONTROL_PARAMETERS; -#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS +#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS //ucInitInfo -#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff +#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff -//ucConfig +//ucConfig #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 -#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 +#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE @@ -1025,7 +1025,7 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF ) - UCHAR ucReserved:1; + UCHAR ucReserved:1; UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E @@ -1040,14 +1040,14 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector - UCHAR ucReserved:1; + UCHAR ucReserved:1; UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) // =1 Dig Transmitter 2 ( Uniphy CD ) // =2 Dig Transmitter 3 ( Uniphy EF ) #endif }ATOM_DIG_TRANSMITTER_CONFIG_V2; -//ucConfig +//ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 @@ -1126,7 +1126,7 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 UCHAR ucReserved[3]; }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; -//ucConfig +//ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 @@ -1156,17 +1156,17 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF -/****************************************************************************/ +/****************************************************************************/ // Structures used by UNIPHYTransmitterControlTable V1.4 // ASIC Families: NI // ucTableFormatRevision=1 // ucTableContentRevision=4 -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_DP_VS_MODE_V4 { UCHAR ucLaneSel; union - { + { UCHAR ucLaneSet; struct { #if ATOM_BIG_ENDIAN @@ -1179,9 +1179,9 @@ typedef struct _ATOM_DP_VS_MODE_V4 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 #endif }; - }; + }; }ATOM_DP_VS_MODE_V4; - + typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 { #if ATOM_BIG_ENDIAN @@ -1220,24 +1220,24 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; UCHAR ucConfig; }; - UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX + UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX UCHAR ucLaneNum; UCHAR ucReserved[3]; }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; -//ucConfig +//ucConfig //Bit0 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 //Bit1 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 //Bit2 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 -#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 +#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 // Bit3 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 -#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 -#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 +#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 +#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 // Bit5:4 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 @@ -1256,13 +1256,13 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 #if ATOM_BIG_ENDIAN UCHAR ucReservd1:1; UCHAR ucHPDSel:3; - UCHAR ucPhyClkSrcId:2; - UCHAR ucCoherentMode:1; + UCHAR ucPhyClkSrcId:2; + UCHAR ucCoherentMode:1; UCHAR ucReserved:1; #else UCHAR ucReserved:1; - UCHAR ucCoherentMode:1; - UCHAR ucPhyClkSrcId:2; + UCHAR ucCoherentMode:1; + UCHAR ucPhyClkSrcId:2; UCHAR ucHPDSel:3; UCHAR ucReservd1:1; #endif @@ -1280,14 +1280,14 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; UCHAR ucConfig; }; - UCHAR ucDigEncoderSel; // indicate DIG front end encoder + UCHAR ucDigEncoderSel; // indicate DIG front end encoder UCHAR ucDPLaneSet; UCHAR ucReserved; UCHAR ucReserved1; }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; //ucPhyId -#define ATOM_PHY_ID_UNIPHYA 0 +#define ATOM_PHY_ID_UNIPHYA 0 #define ATOM_PHY_ID_UNIPHYB 1 #define ATOM_PHY_ID_UNIPHYC 2 #define ATOM_PHY_ID_UNIPHYD 3 @@ -1317,12 +1317,12 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 #define DP_LANE_SET__0DB_0_6V 0x01 #define DP_LANE_SET__0DB_0_8V 0x02 #define DP_LANE_SET__0DB_1_2V 0x03 -#define DP_LANE_SET__3_5DB_0_4V 0x08 +#define DP_LANE_SET__3_5DB_0_4V 0x08 #define DP_LANE_SET__3_5DB_0_6V 0x09 #define DP_LANE_SET__3_5DB_0_8V 0x0a #define DP_LANE_SET__6DB_0_4V 0x10 #define DP_LANE_SET__6DB_0_6V 0x11 -#define DP_LANE_SET__9_5DB_0_4V 0x18 +#define DP_LANE_SET__9_5DB_0_4V 0x18 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; // Bit1 @@ -1334,7 +1334,7 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 -#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 +#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c // Bit6:4 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 @@ -1351,25 +1351,25 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 -/****************************************************************************/ +/****************************************************************************/ // Structures used by ExternalEncoderControlTable V1.3 // ASIC Families: Evergreen, Llano, NI // ucTableFormatRevision=1 // ucTableContentRevision=3 -/****************************************************************************/ +/****************************************************************************/ typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 { union{ - USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT + USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT USHORT usConnectorId; // connector id, valid when ucAction = INIT }; - UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT - UCHAR ucAction; // + UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT + UCHAR ucAction; // UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT - UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT + UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP - UCHAR ucReserved; + UCHAR ucReserved; }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; // ucAction @@ -1399,29 +1399,29 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; -/****************************************************************************/ +/****************************************************************************/ // Structures used by DAC1OuputControlTable // DAC2OuputControlTable // LVTMAOutputControlTable (Before DEC30) // TMDSAOutputControlTable (Before DEC30) -/****************************************************************************/ +/****************************************************************************/ typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE // When the display is LCD, in addition to above: // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| // ATOM_LCD_SELFTEST_STOP - + UCHAR aucPadding[3]; // padding to DWORD aligned }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS -#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION -#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS +#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS @@ -1443,9 +1443,9 @@ typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by BlankCRTCTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _BLANK_CRTC_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 @@ -1456,22 +1456,22 @@ typedef struct _BLANK_CRTC_PARAMETERS }BLANK_CRTC_PARAMETERS; #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by EnableCRTCTable // EnableCRTCMemReqTable // UpdateCRTC_DoubleBufferRegistersTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_CRTC_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 - UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE + UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE UCHAR ucPadding[2]; }ENABLE_CRTC_PARAMETERS; #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetCRTC_OverScanTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_CRTC_OVERSCAN_PARAMETERS { USHORT usOverscanRight; // right @@ -1483,9 +1483,9 @@ typedef struct _SET_CRTC_OVERSCAN_PARAMETERS }SET_CRTC_OVERSCAN_PARAMETERS; #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetCRTC_ReplicationTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_CRTC_REPLICATION_PARAMETERS { UCHAR ucH_Replication; // horizontal replication @@ -1495,9 +1495,9 @@ typedef struct _SET_CRTC_REPLICATION_PARAMETERS }SET_CRTC_REPLICATION_PARAMETERS; #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by SelectCRTC_SourceTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SELECT_CRTC_SOURCE_PARAMETERS { UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 @@ -1515,7 +1515,7 @@ typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 }SELECT_CRTC_SOURCE_PARAMETERS_V2; //ucEncoderID -//#define ASIC_INT_DAC1_ENCODER_ID 0x00 +//#define ASIC_INT_DAC1_ENCODER_ID 0x00 //#define ASIC_INT_TV_ENCODER_ID 0x02 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 @@ -1534,10 +1534,10 @@ typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 //#define ATOM_ENCODER_MODE_CV 14 //#define ATOM_ENCODER_MODE_CRT 15 -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetPixelClockTable -// GetPixelClockTable -/****************************************************************************/ +// GetPixelClockTable +/****************************************************************************/ //Major revision=1., Minor revision=1 typedef struct _PIXEL_CLOCK_PARAMETERS { @@ -1545,7 +1545,7 @@ typedef struct _PIXEL_CLOCK_PARAMETERS // 0 means disable PPLL USHORT usRefDiv; // Reference divider USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider + UCHAR ucPostDiv; // post divider UCHAR ucFracFbDiv; // fractional feedback divider UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER @@ -1565,7 +1565,7 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V2 // 0 means disable PPLL USHORT usRefDiv; // Reference divider USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider + UCHAR ucPostDiv; // post divider UCHAR ucFracFbDiv; // fractional feedback divider UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER @@ -1612,7 +1612,7 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V3 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. USHORT usRefDiv; // Reference divider USHORT usFbDiv; // feedback divider - UCHAR ucPostDiv; // post divider + UCHAR ucPostDiv; // post divider UCHAR ucFracFbDiv; // fractional feedback divider UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h @@ -1631,25 +1631,25 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V3 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 { - UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to + UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case. union{ UCHAR ucReserved; UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. }; USHORT usPixelClock; // target the pixel clock to drive the CRTC timing - // 0 means disable PPLL/DCPLL. - USHORT usFbDiv; // feedback divider integer part. - UCHAR ucPostDiv; // post divider. + // 0 means disable PPLL/DCPLL. + USHORT usFbDiv; // feedback divider integer part. + UCHAR ucPostDiv; // post divider. UCHAR ucRefDiv; // Reference divider UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL - UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, - // indicate which graphic encoder will be used. - UCHAR ucEncoderMode; // Encoder mode: - UCHAR ucMiscInfo; // bit[0]= Force program PPLL - // bit[1]= when VGA timing is used. + UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + UCHAR ucEncoderMode; // Encoder mode: + UCHAR ucMiscInfo; // bit[0]= Force program PPLL + // bit[1]= when VGA timing is used. // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp - // bit[4]= RefClock source for PPLL. + // bit[4]= RefClock source for PPLL. // =0: XTLAIN( default mode ) // =1: other external clock source, which is pre-defined // by VBIOS depend on the feature required. @@ -1669,14 +1669,14 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V5 typedef struct _CRTC_PIXEL_CLOCK_FREQ { #if ATOM_BIG_ENDIAN - ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to + ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case. - ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. + ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. #else - ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. + ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. - ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to + ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to // drive the pixel clock. not used for DCPLL case. #endif }CRTC_PIXEL_CLOCK_FREQ; @@ -1684,22 +1684,22 @@ typedef struct _CRTC_PIXEL_CLOCK_FREQ typedef struct _PIXEL_CLOCK_PARAMETERS_V6 { union{ - CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency + CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency ULONG ulDispEngClkFreq; // dispclk frequency }; - USHORT usFbDiv; // feedback divider integer part. - UCHAR ucPostDiv; // post divider. + USHORT usFbDiv; // feedback divider integer part. + UCHAR ucPostDiv; // post divider. UCHAR ucRefDiv; // Reference divider UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL - UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, - // indicate which graphic encoder will be used. - UCHAR ucEncoderMode; // Encoder mode: - UCHAR ucMiscInfo; // bit[0]= Force program PPLL - // bit[1]= when VGA timing is used. + UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + UCHAR ucEncoderMode; // Encoder mode: + UCHAR ucMiscInfo; // bit[0]= Force program PPLL + // bit[1]= when VGA timing is used. // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp - // bit[4]= RefClock source for PPLL. + // bit[4]= RefClock source for PPLL. // =0: XTLAIN( default mode ) - // =1: other external clock source, which is pre-defined + // =1: other external clock source, which is pre-defined // by VBIOS depend on the feature required. // bit[7:5]: reserved. ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) @@ -1735,9 +1735,9 @@ typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; -/****************************************************************************/ +/****************************************************************************/ // Structures used by AdjustDisplayPllTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS { USHORT usPixelClock; @@ -1782,21 +1782,21 @@ typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider - UCHAR ucReserved[2]; + UCHAR ucReserved[2]; }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 { - union + union { ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; }; } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; -/****************************************************************************/ +/****************************************************************************/ // Structures used by EnableYUVTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_YUV_PARAMETERS { UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) @@ -1805,27 +1805,27 @@ typedef struct _ENABLE_YUV_PARAMETERS }ENABLE_YUV_PARAMETERS; #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by GetMemoryClockTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _GET_MEMORY_CLOCK_PARAMETERS { ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit } GET_MEMORY_CLOCK_PARAMETERS; #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by GetEngineClockTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _GET_ENGINE_CLOCK_PARAMETERS { ULONG ulReturnEngineClock; // current engine speed in 10KHz unit } GET_ENGINE_CLOCK_PARAMETERS; #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Following Structures and constant may be obsolete -/****************************************************************************/ +/****************************************************************************/ //Maxium 8 bytes,the data read in will be placed in the parameter space. //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS @@ -1850,7 +1850,7 @@ typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS { USHORT usPrescale; //Ratio between Engine clock and I2C clock USHORT usByteOffset; //Write to which byte - //Upper portion of usByteOffset is Format of data + //Upper portion of usByteOffset is Format of data //1bytePS+offsetPS //2bytesPS+offsetPS //blockID+offsetPS @@ -1876,18 +1876,18 @@ typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structures used by PowerConnectorDetectionTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS { UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected - UCHAR ucPwrBehaviorId; + UCHAR ucPwrBehaviorId; USHORT usPwrBudget; //how much power currently boot to in unit of watt }POWER_CONNECTOR_DETECTION_PARAMETERS; typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION -{ +{ UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected UCHAR ucReserved; USHORT usPwrBudget; //how much power currently boot to in unit of watt @@ -1896,12 +1896,12 @@ typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION /****************************LVDS SS Command Table Definitions**********************/ -/****************************************************************************/ +/****************************************************************************/ // Structures used by EnableSpreadSpectrumOnPPLLTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_LVDS_SS_PARAMETERS { - USHORT usSpreadSpectrumPercentage; + USHORT usSpreadSpectrumPercentage; UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE @@ -1911,7 +1911,7 @@ typedef struct _ENABLE_LVDS_SS_PARAMETERS //ucTableFormatRevision=1,ucTableContentRevision=2 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 { - USHORT usSpreadSpectrumPercentage; + USHORT usSpreadSpectrumPercentage; UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD UCHAR ucSpreadSpectrumStep; // UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE @@ -1935,12 +1935,12 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 { USHORT usSpreadSpectrumPercentage; - UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. - // Bit[1]: 1-Ext. 0-Int. + UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. + // Bit[1]: 1-Ext. 0-Int. // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL // Bits[7:4] reserved UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] + USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; @@ -1960,15 +1960,15 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 { USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 - UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. - // Bit[1]: 1-Ext. 0-Int. + UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. + // Bit[1]: 1-Ext. 0-Int. // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL // Bits[7:4] reserved UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] + USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; - + #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 @@ -1989,14 +1989,14 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION { PIXEL_CLOCK_PARAMETERS sPCLKInput; - ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion + ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion }SET_PIXEL_CLOCK_PS_ALLOCATION; #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION -/****************************************************************************/ +/****************************************************************************/ // Structures used by ### -/****************************************************************************/ +/****************************************************************************/ typedef struct _MEMORY_TRAINING_PARAMETERS { ULONG ulTargetMemoryClock; //In 10Khz unit @@ -2007,11 +2007,11 @@ typedef struct _MEMORY_TRAINING_PARAMETERS /****************************LVDS and other encoder command table definitions **********************/ -/****************************************************************************/ +/****************************************************************************/ // Structures used by LVDSEncoderControlTable (Before DCE30) // LVTMAEncoderControlTable (Before DCE30) // TMDSAEncoderControlTable (Before DCE30) -/****************************************************************************/ +/****************************************************************************/ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient @@ -2024,7 +2024,7 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS }LVDS_ENCODER_CONTROL_PARAMETERS; #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS - + #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS @@ -2064,10 +2064,10 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 - + #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 - + #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 @@ -2080,18 +2080,18 @@ typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 -/****************************************************************************/ +/****************************************************************************/ // Structures used by ### -/****************************************************************************/ +/****************************************************************************/ typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS -{ +{ UCHAR ucEnable; // Enable or Disable External TMDS encoder UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} UCHAR ucPadding[2]; }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION -{ +{ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; @@ -2099,7 +2099,7 @@ typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 -{ +{ ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; @@ -2110,9 +2110,9 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ // Structures used by DVOEncoderControlTable -/****************************************************************************/ +/****************************************************************************/ //ucTableFormatRevision=1,ucTableContentRevision=3 //ucDVOConfig: @@ -2126,7 +2126,7 @@ typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { - USHORT usPixelClock; + USHORT usPixelClock; UCHAR ucDVOConfig; UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT UCHAR ucReseved[4]; @@ -2135,7 +2135,7 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 { - USHORT usPixelClock; + USHORT usPixelClock; UCHAR ucDVOConfig; UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR @@ -2145,7 +2145,7 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 //ucTableFormatRevision=1 -//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for +//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for // bit1=0: non-coherent mode // =1: coherent mode @@ -2192,9 +2192,9 @@ typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 #define PANEL_ENCODER_75FRC_E 0x00 #define PANEL_ENCODER_75FRC_F 0x80 -/****************************************************************************/ +/****************************************************************************/ // Structures used by SetVoltageTable -/****************************************************************************/ +/****************************************************************************/ #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 @@ -2215,7 +2215,7 @@ typedef struct _SET_VOLTAGE_PARAMETERS UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ UCHAR ucVoltageMode; // To set all, to set source A or source B or ... UCHAR ucVoltageIndex; // An index to tell which voltage level - UCHAR ucReserved; + UCHAR ucReserved; }SET_VOLTAGE_PARAMETERS; typedef struct _SET_VOLTAGE_PARAMETERS_V2 @@ -2245,7 +2245,7 @@ typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 -#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 +#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 // define vitual voltage id in usVoltageLevel #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 @@ -2268,7 +2268,7 @@ typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 { UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info - USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id + USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id ULONG ulReserved; }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; @@ -2307,14 +2307,14 @@ typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 { UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info - USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id + USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; // New in GetVoltageInfo v1.2 ucVoltageMode -#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 +#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 -// New Added from CI Hawaii for EVV feature +// New Added from CI Hawaii for EVV feature typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 { USHORT usVoltageLevel; // real voltage level in unit of mv @@ -2322,9 +2322,9 @@ typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 ULONG ulReseved; }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; -/****************************************************************************/ +/****************************************************************************/ // Structures used by TVEncoderControlTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _TV_ENCODER_CONTROL_PARAMETERS { USHORT usPixelClock; // in 10KHz; for bios convenient @@ -2335,28 +2335,28 @@ typedef struct _TV_ENCODER_CONTROL_PARAMETERS typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION { - TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; + TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one }TV_ENCODER_CONTROL_PS_ALLOCATION; //==============================Data Table Portion==================================== -/****************************************************************************/ +/****************************************************************************/ // Structure used in Data.mtb -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES { USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! - USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios + USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios USHORT StandardVESA_Timing; // Only used by Bios USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 USHORT PaletteData; // Only used by BIOS - USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info + USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 - USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 + USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 USHORT SupportedDevicesInfo; // Will be obsolete from R600 - USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 + USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 USHORT VESA_ToInternalModeLUT; // Only used by Bios @@ -2383,22 +2383,22 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES }ATOM_MASTER_LIST_OF_DATA_TABLES; typedef struct _ATOM_MASTER_DATA_TABLE -{ - ATOM_COMMON_TABLE_HEADER sHeader; +{ + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; }ATOM_MASTER_DATA_TABLE; -// For backward compatible +// For backward compatible #define LVDS_Info LCD_Info #define DAC_Info PaletteData #define TMDS_Info DIGTransmitterInfo -/****************************************************************************/ +/****************************************************************************/ // Structure used in MultimediaCapabilityInfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulSignature; // HW info table signature string "$ATI" UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) @@ -2406,9 +2406,9 @@ typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO UCHAR ucHostPortInfo; // Provides host port configuration information }ATOM_MULTIMEDIA_CAPABILITY_INFO; -/****************************************************************************/ +/****************************************************************************/ // Structure used in MultimediaConfigInfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO { ATOM_COMMON_TABLE_HEADER sHeader; @@ -2428,20 +2428,20 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO }ATOM_MULTIMEDIA_CONFIG_INFO; -/****************************************************************************/ +/****************************************************************************/ // Structures used in FirmwareInfoTable -/****************************************************************************/ +/****************************************************************************/ // usBIOSCapability Definition: -// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; -// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; -// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; +// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; +// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; +// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; // Others: Reserved #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 -#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. -#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. +#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. +#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 @@ -2505,7 +2505,7 @@ typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS typedef struct _ATOM_FIRMWARE_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2530,8 +2530,8 @@ typedef struct _ATOM_FIRMWARE_INFO USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit UCHAR ucDesign_ID; //Indicate what is the board design UCHAR ucMemoryModule_ID; //Indicate what is the board design @@ -2539,7 +2539,7 @@ typedef struct _ATOM_FIRMWARE_INFO typedef struct _ATOM_FIRMWARE_INFO_V1_2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2566,8 +2566,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_2 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit UCHAR ucDesign_ID; //Indicate what is the board design UCHAR ucMemoryModule_ID; //Indicate what is the board design @@ -2575,7 +2575,7 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_2 typedef struct _ATOM_FIRMWARE_INFO_V1_3 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2603,8 +2603,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_3 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit UCHAR ucDesign_ID; //Indicate what is the board design UCHAR ucMemoryModule_ID; //Indicate what is the board design @@ -2612,7 +2612,7 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_3 typedef struct _ATOM_FIRMWARE_INFO_V1_4 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2641,8 +2641,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_4 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usReferenceClock; //In 10Khz unit - USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit + USHORT usReferenceClock; //In 10Khz unit + USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit UCHAR ucDesign_ID; //Indicate what is the board design UCHAR ucMemoryModule_ID; //Indicate what is the board design @@ -2651,7 +2651,7 @@ typedef struct _ATOM_FIRMWARE_INFO_V1_4 //the structure below to be used from Cypress typedef struct _ATOM_FIRMWARE_INFO_V2_1 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit @@ -2680,8 +2680,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_1 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usCoreReferenceClock; //In 10Khz unit - USHORT usMemoryReferenceClock; //In 10Khz unit + USHORT usCoreReferenceClock; //In 10Khz unit + USHORT usMemoryReferenceClock; //In 10Khz unit USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock UCHAR ucMemoryModule_ID; //Indicate what is the board design UCHAR ucReserved4[3]; @@ -2692,17 +2692,17 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_1 //ucTableContentRevision=2 typedef struct _ATOM_FIRMWARE_INFO_V2_2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulFirmwareRevision; ULONG ulDefaultEngineClock; //In 10Khz unit ULONG ulDefaultMemoryClock; //In 10Khz unit - ULONG ulSPLL_OutputFreq; //In 10Khz unit + ULONG ulSPLL_OutputFreq; //In 10Khz unit ULONG ulGPUPLL_OutputFreq; //In 10Khz unit ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? - ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. + ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. UCHAR ucReserved3; //Was ucASICMaxTemperature; UCHAR ucMinAllowedBL_Level; USHORT usBootUpVDDCVoltage; //In MV unit @@ -2719,8 +2719,8 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_2 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; - USHORT usCoreReferenceClock; //In 10Khz unit - USHORT usMemoryReferenceClock; //In 10Khz unit + USHORT usCoreReferenceClock; //In 10Khz unit + USHORT usMemoryReferenceClock; //In 10Khz unit USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock UCHAR ucMemoryModule_ID; //Indicate what is the board design UCHAR ucReserved9[3]; @@ -2736,9 +2736,9 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_2 #define REMOTE_DISPLAY_DISABLE 0x00 #define REMOTE_DISPLAY_ENABLE 0x01 -/****************************************************************************/ +/****************************************************************************/ // Structures used in IntegratedSystemInfoTable -/****************************************************************************/ +/****************************************************************************/ #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 #define IGP_CAP_FLAG_AC_CARD 0x4 #define IGP_CAP_FLAG_SDVO_CARD 0x8 @@ -2746,7 +2746,7 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_2 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulBootUpEngineClock; //in 10kHz unit ULONG ulBootUpMemoryClock; //in 10kHz unit ULONG ulMaxSystemMemoryClock; //in 10kHz unit @@ -2754,8 +2754,8 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO UCHAR ucNumberOfCyclesInPeriodHi; UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. USHORT usReserved1; - USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage - USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage + USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage + USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage ULONG ulReserved[2]; USHORT usFSBClock; //In MHz unit @@ -2769,22 +2769,22 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO UCHAR ucMaxNBVoltage; UCHAR ucMinNBVoltage; UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved - UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod + UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime UCHAR ucHTLinkWidth; //16 bit vs. 8 bit - UCHAR ucMaxNBVoltageHigh; + UCHAR ucMaxNBVoltageHigh; UCHAR ucMinNBVoltageHigh; }ATOM_INTEGRATED_SYSTEM_INFO; /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO -ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock +ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 -ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 +ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 For AMD IGP,for now this can be 0 -usFSBClock: For Intel IGP,it's FSB Freq +usFSBClock: For Intel IGP,it's FSB Freq For AMD IGP,it's HT Link Speed usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 @@ -2795,8 +2795,8 @@ VC:Voltage Control ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. -ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. -ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 +ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. +ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. @@ -2809,7 +2809,7 @@ usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes t /* The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; -Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. +Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. SW components can access the IGP system infor structure in the same way as before @@ -2856,23 +2856,23 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. ULONG ulReserved3[96]; //must be 0x0 -}ATOM_INTEGRATED_SYSTEM_INFO_V2; +}ATOM_INTEGRATED_SYSTEM_INFO_V2; /* ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock -ulSystemConfig: -Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; +ulSystemConfig: +Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state =0: system boots up at driver control state. Power state depends on PowerPlay table. Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. Bit[3]=1: Only one power state(Performance) will be supported. =0: Multiple power states supported from PowerPlay table. -Bit[4]=1: CLMC is supported and enabled on current system. - =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. -Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. +Bit[4]=1: CLMC is supported and enabled on current system. + =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. +Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. =0: Voltage settings is determined by powerplay table. @@ -2895,7 +2895,7 @@ ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (A in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. - [15:8] - Lane configuration attribute; + [15:8] - Lane configuration attribute; [23:16]- Connector type, possible value: CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D @@ -2910,7 +2910,7 @@ For IGP, Hypermemory is the only memory type showed in CCC. ucUMAChannelNumber: how many channels for the UMA; -ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin +ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin ucDockingPinBit: which bit in this register to read the pin status; ucDockingPinPolarity:Polarity of the pin when docked; @@ -2918,7 +2918,7 @@ ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Phara usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. -usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. +usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 @@ -2927,14 +2927,14 @@ usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. ulHTLinkFreq: Bootup HT link Frequency in 10Khz. -usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. +usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. + If CDLW enabled, both upstream and downstream width should be the same during bootup. +usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. If CDLW enabled, both upstream and downstream width should be the same during bootup. -usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. - If CDLW enabled, both upstream and downstream width should be the same during bootup. -usUMASyncStartDelay: Memory access latency, required for watermark calculation +usUMASyncStartDelay: Memory access latency, required for watermark calculation usUMADataReturnTime: Memory access latency, required for watermark calculation -usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us +usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) @@ -2942,7 +2942,7 @@ for Griffin or Greyhound. SBIOS needs to convert to actual time by: if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. - This must be less than or equal to ulHTLinkFreq(bootup frequency). + This must be less than or equal to ulHTLinkFreq(bootup frequency). ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. This must be less than or equal to ulHighVoltageHTLinkFreq. @@ -2952,7 +2952,7 @@ usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to rep usMinDownStreamHTLinkWidth: same as above. */ -// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition +// ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 @@ -2964,7 +2964,7 @@ usMinDownStreamHTLinkWidth: same as above. #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 -#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 +#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 @@ -2993,7 +2993,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 { ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulBootUpEngineClock; //in 10kHz unit - ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. + ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge ULONG ulBootUpUMAClock; //in 10kHz unit ULONG ulReserved1[8]; //must be 0x0 for the reserved @@ -3021,7 +3021,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications ULONG ulReserved6[61]; //must be 0x0 -}ATOM_INTEGRATED_SYSTEM_INFO_V5; +}ATOM_INTEGRATED_SYSTEM_INFO_V5; #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 @@ -3039,7 +3039,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable -#define ASIC_INT_DAC1_ENCODER_ID 0x00 +#define ASIC_INT_DAC1_ENCODER_ID 0x00 #define ASIC_INT_TV_ENCODER_ID 0x02 #define ASIC_INT_DIG1_ENCODER_ID 0x03 #define ASIC_INT_DAC2_ENCODER_ID 0x04 @@ -3056,15 +3056,15 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 //define Encoder attribute #define ATOM_ANALOG_ENCODER 0 -#define ATOM_DIGITAL_ENCODER 1 -#define ATOM_DP_ENCODER 2 +#define ATOM_DIGITAL_ENCODER 1 +#define ATOM_DP_ENCODER 2 #define ATOM_ENCODER_ENUM_MASK 0x70 #define ATOM_ENCODER_ENUM_ID1 0x00 #define ATOM_ENCODER_ENUM_ID2 0x10 #define ATOM_ENCODER_ENUM_ID3 0x20 #define ATOM_ENCODER_ENUM_ID4 0x30 -#define ATOM_ENCODER_ENUM_ID5 0x40 +#define ATOM_ENCODER_ENUM_ID5 0x40 #define ATOM_ENCODER_ENUM_ID6 0x50 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 @@ -3162,8 +3162,8 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported -// -// +// +// /****************************************************************************/ /* Structure used in MclkSS_InfoTable */ @@ -3196,11 +3196,11 @@ typedef union _ATOM_I2C_ID_CONFIG_ACCESS ATOM_I2C_ID_CONFIG sbfAccess; UCHAR ucAccess; }ATOM_I2C_ID_CONFIG_ACCESS; - -/****************************************************************************/ + +/****************************************************************************/ // Structure used in GPIO_I2C_InfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_GPIO_I2C_ASSIGMENT { USHORT usClkMaskRegisterIndex; @@ -3225,20 +3225,20 @@ typedef struct _ATOM_GPIO_I2C_ASSIGMENT }ATOM_GPIO_I2C_ASSIGMENT; typedef struct _ATOM_GPIO_I2C_INFO -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; }ATOM_GPIO_I2C_INFO; -/****************************************************************************/ +/****************************************************************************/ // Common Structure used in other structures -/****************************************************************************/ +/****************************************************************************/ #ifndef _H2INC - + //Please don't add or expand this bitfield structure below, this one will retire soon.! typedef struct _ATOM_MODE_MISC_INFO -{ +{ #if ATOM_BIG_ENDIAN USHORT Reserved:6; USHORT RGB888:1; @@ -3262,23 +3262,23 @@ typedef struct _ATOM_MODE_MISC_INFO USHORT Interlace:1; USHORT DoubleClock:1; USHORT RGB888:1; - USHORT Reserved:6; + USHORT Reserved:6; #endif }ATOM_MODE_MISC_INFO; - + typedef union _ATOM_MODE_MISC_INFO_ACCESS -{ +{ ATOM_MODE_MISC_INFO sbfAccess; USHORT usAccess; }ATOM_MODE_MISC_INFO_ACCESS; - + #else - + typedef union _ATOM_MODE_MISC_INFO_ACCESS -{ +{ USHORT usAccess; }ATOM_MODE_MISC_INFO_ACCESS; - + #endif // usModeMiscInfo- @@ -3296,7 +3296,7 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS //usRefreshRate- #define ATOM_REFRESH_43 43 #define ATOM_REFRESH_47 47 -#define ATOM_REFRESH_56 56 +#define ATOM_REFRESH_56 56 #define ATOM_REFRESH_60 60 #define ATOM_REFRESH_65 65 #define ATOM_REFRESH_70 70 @@ -3315,29 +3315,29 @@ typedef union _ATOM_MODE_MISC_INFO_ACCESS // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW // VESA_BORDER = EDID_BORDER -/****************************************************************************/ +/****************************************************************************/ // Structure used in SetCRTC_UsingDTDTimingTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS { USHORT usH_Size; USHORT usH_Blanking_Time; USHORT usV_Size; - USHORT usV_Blanking_Time; + USHORT usV_Blanking_Time; USHORT usH_SyncOffset; USHORT usH_SyncWidth; USHORT usV_SyncOffset; USHORT usV_SyncWidth; - ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; + ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; UCHAR ucH_Border; // From DFP EDID UCHAR ucV_Border; - UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 + UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 UCHAR ucPadding[3]; }SET_CRTC_USING_DTD_TIMING_PARAMETERS; -/****************************************************************************/ +/****************************************************************************/ // Structure used in SetCRTC_TimingTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_CRTC_TIMING_PARAMETERS { USHORT usH_Total; // horizontal total @@ -3358,11 +3358,11 @@ typedef struct _SET_CRTC_TIMING_PARAMETERS }SET_CRTC_TIMING_PARAMETERS; #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS -/****************************************************************************/ +/****************************************************************************/ // Structure used in StandardVESA_TimingTable -// AnalogTV_InfoTable +// AnalogTV_InfoTable // ComponentVideoInfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_MODE_TIMING { USHORT usCRTC_H_Total; @@ -3390,7 +3390,7 @@ typedef struct _ATOM_DTD_FORMAT USHORT usHActive; USHORT usHBlanking_Time; USHORT usVActive; - USHORT usVBlanking_Time; + USHORT usVBlanking_Time; USHORT usHSyncOffset; USHORT usHSyncWidth; USHORT usVSyncOffset; @@ -3404,10 +3404,10 @@ typedef struct _ATOM_DTD_FORMAT UCHAR ucRefreshRate; }ATOM_DTD_FORMAT; -/****************************************************************************/ -// Structure used in LVDS_InfoTable +/****************************************************************************/ +// Structure used in LVDS_InfoTable // * Need a document to describe this table -/****************************************************************************/ +/****************************************************************************/ #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 @@ -3417,7 +3417,7 @@ typedef struct _ATOM_DTD_FORMAT //ucTableContentRevision=1 typedef struct _ATOM_LVDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_DTD_FORMAT sLCDTiming; USHORT usModePatchTableOffset; USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. @@ -3437,7 +3437,7 @@ typedef struct _ATOM_LVDS_INFO //ucTableContentRevision=2 typedef struct _ATOM_LVDS_INFO_V12 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_DTD_FORMAT sLCDTiming; USHORT usExtInfoTableOffset; USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. @@ -3453,15 +3453,15 @@ typedef struct _ATOM_LVDS_INFO_V12 UCHAR ucSS_Id; USHORT usLCDVenderID; USHORT usLCDProductID; - UCHAR ucLCDPanel_SpecialHandlingCap; + UCHAR ucLCDPanel_SpecialHandlingCap; UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable UCHAR ucReserved[2]; }ATOM_LVDS_INFO_V12; //Definitions for ucLCDPanel_SpecialHandlingCap: -//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. -//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL +//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. +//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL #define LCDPANEL_CAP_READ_EDID 0x1 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together @@ -3486,21 +3486,21 @@ typedef struct _ATOM_LVDS_INFO_V12 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 -// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} +// Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} #define PANEL_RANDOM_DITHER 0x80 #define PANEL_RANDOM_DITHER_MASK 0x80 -#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this +#define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this -/****************************************************************************/ +/****************************************************************************/ // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 // ASIC Families: NI // ucTableFormatRevision=1 // ucTableContentRevision=3 -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_LCD_INFO_V13 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_DTD_FORMAT sLCDTiming; USHORT usExtInfoTableOffset; USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. @@ -3509,18 +3509,18 @@ typedef struct _ATOM_LCD_INFO_V13 // Bit0: {=0:single, =1:dual}, // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, // Bit3:2: {Grey level} - // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) - // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? + // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) + // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? UCHAR ucPanelDefaultRefreshRate; UCHAR ucPanelIdentification; UCHAR ucSS_Id; USHORT usLCDVenderID; USHORT usLCDProductID; - UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 + UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) - // Bit7-3: Reserved + // Bit7-3: Reserved UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 @@ -3539,13 +3539,13 @@ typedef struct _ATOM_LCD_INFO_V13 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h - USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. + USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. UCHAR uceDPToLVDSRxId; UCHAR ucLcdReservd; ULONG ulReserved[2]; -}ATOM_LCD_INFO_V13; +}ATOM_LCD_INFO_V13; -#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 +#define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 //Definitions for ucLCD_Misc #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 @@ -3566,11 +3566,11 @@ typedef struct _ATOM_LCD_INFO_V13 // 1 0 1 - 14 Bits per Primary Color // 1 1 0 - 16 Bits per Primary Color // 1 1 1 - Reserved - + //Definitions for ucLCDPanel_SpecialHandlingCap: -//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. -//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL +//Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. +//Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together @@ -3582,7 +3582,7 @@ typedef struct _ATOM_LCD_INFO_V13 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version //uceDPToLVDSRxId -#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip +#define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init @@ -3599,7 +3599,7 @@ typedef struct _ATOM_LCD_RTS_RECORD UCHAR ucRTSValue; }ATOM_LCD_RTS_RECORD; -//!! If the record below exits, it shoud always be the first record for easy use in command table!!! +//!! If the record below exits, it shoud always be the first record for easy use in command table!!! // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. typedef struct _ATOM_LCD_MODE_CONTROL_CAP { @@ -3639,7 +3639,7 @@ typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD //ucTableContentRevision=2 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT { - USHORT usSpreadSpectrumPercentage; + USHORT usSpreadSpectrumPercentage; UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD UCHAR ucSS_Step; UCHAR ucSS_Delay; @@ -3649,8 +3649,8 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; #define ATOM_MAX_SS_ENTRY 16 -#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. -#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. +#define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. +#define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz @@ -3662,18 +3662,18 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT #define ATOM_INTERNAL_SS_MASK 0x00000000 #define ATOM_EXTERNAL_SS_MASK 0x00000002 #define EXEC_SS_STEP_SIZE_SHIFT 2 -#define EXEC_SS_DELAY_SHIFT 4 +#define EXEC_SS_DELAY_SHIFT 4 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 typedef struct _ATOM_SPREAD_SPECTRUM_INFO -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; }ATOM_SPREAD_SPECTRUM_INFO; -/****************************************************************************/ +/****************************************************************************/ // Structure used in AnalogTV_InfoTable (Top level) -/****************************************************************************/ +/****************************************************************************/ //ucTVBootUpDefaultStd definition: //ATOM_TV_NTSC 1 @@ -3700,9 +3700,9 @@ typedef struct _ATOM_SPREAD_SPECTRUM_INFO typedef struct _ATOM_ANALOG_TV_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucTV_BootUpDefaultStandard; UCHAR ucExt_TV_ASIC_ID; UCHAR ucExt_TV_ASIC_SlaveAddr; /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ @@ -3713,9 +3713,9 @@ typedef struct _ATOM_ANALOG_TV_INFO typedef struct _ATOM_ANALOG_TV_INFO_V1_2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucTV_SupportedStandard; - UCHAR ucTV_BootUpDefaultStandard; + UCHAR ucTV_BootUpDefaultStandard; UCHAR ucExt_TV_ASIC_ID; UCHAR ucExt_TV_ASIC_SlaveAddr; ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; @@ -3723,9 +3723,9 @@ typedef struct _ATOM_ANALOG_TV_INFO_V1_2 typedef struct _ATOM_DPCD_INFO { - UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 + UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane - UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP + UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) }ATOM_DPCD_INFO; @@ -3738,7 +3738,7 @@ typedef struct _ATOM_DPCD_INFO // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR -// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX +// To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX #ifndef VESA_MEMORY_IN_64K_BLOCK #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) @@ -3748,11 +3748,11 @@ typedef struct _ATOM_DPCD_INFO #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes #define ATOM_HWICON_INFOTABLE_SIZE 32 #define MAX_DTD_MODE_IN_VRAM 6 -#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) +#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) //20 bytes for Encoder Type and DPCD in STD EDID area -#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) -#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) +#define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) +#define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) #define ATOM_HWICON1_SURFACE_ADDR 0 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) @@ -3805,12 +3805,12 @@ typedef struct _ATOM_DPCD_INFO #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) -#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) -#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 +#define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) +#define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 //The size below is in Kb! #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) - + #define ATOM_VRAM_RESERVE_V2_SIZE 32 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L @@ -3818,15 +3818,15 @@ typedef struct _ATOM_DPCD_INFO #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 -/***********************************************************************************/ +/***********************************************************************************/ // Structure used in VRAM_UsageByFirmwareTable // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm -// at running time. -// note2: From RV770, the memory is more than 32bit addressable, so we will change -// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains -// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware +// at running time. +// note2: From RV770, the memory is more than 32bit addressable, so we will change +// ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains +// exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware // (in offset to start of memory address) is KB aligned instead of byte aligend. -/***********************************************************************************/ +/***********************************************************************************/ // Note3: /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: @@ -3842,7 +3842,7 @@ else //Non VGA case CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ -/***********************************************************************************/ +/***********************************************************************************/ #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO @@ -3854,11 +3854,11 @@ typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; }ATOM_VRAM_USAGE_BY_FIRMWARE; -// change verion to 1.5, when allow driver to allocate the vram area for command table access. +// change verion to 1.5, when allow driver to allocate the vram area for command table access. typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 { ULONG ulStartAddrUsedByFirmware; @@ -3868,13 +3868,13 @@ typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; -/****************************************************************************/ +/****************************************************************************/ // Structure used in GPIO_Pin_LUTTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_GPIO_PIN_ASSIGNMENT { USHORT usGpioPin_AIndex; @@ -3896,9 +3896,9 @@ typedef struct _ATOM_GPIO_PIN_LUT ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; }ATOM_GPIO_PIN_LUT; -/****************************************************************************/ -// Structure used in ComponentVideoInfoTable -/****************************************************************************/ +/****************************************************************************/ +// Structure used in ComponentVideoInfoTable +/****************************************************************************/ #define GPIO_PIN_ACTIVE_HIGH 0x1 #define MAX_SUPPORTED_CV_STANDARDS 5 @@ -3926,17 +3926,17 @@ typedef struct _ATOM_GPIO_INFO //Line 3 out put 5V. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 -#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 +#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 -//Line 3 out put 2.2V +//Line 3 out put 2.2V #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 //Line 3 out put 0V #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 -#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 +#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] @@ -3988,11 +3988,11 @@ typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 -/****************************************************************************/ +/****************************************************************************/ // Structure used in object_InfoTable -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_OBJECT_HEADER -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; USHORT usConnectorObjectTableOffset; @@ -4003,7 +4003,7 @@ typedef struct _ATOM_OBJECT_HEADER }ATOM_OBJECT_HEADER; typedef struct _ATOM_OBJECT_HEADER_V3 -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; USHORT usConnectorObjectTableOffset; @@ -4016,20 +4016,20 @@ typedef struct _ATOM_OBJECT_HEADER_V3 typedef struct _ATOM_DISPLAY_OBJECT_PATH { - USHORT usDeviceTag; //supported device + USHORT usDeviceTag; //supported device USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH - USHORT usConnObjectId; //Connector Object ID - USHORT usGPUObjectId; //GPU ID + USHORT usConnObjectId; //Connector Object ID + USHORT usGPUObjectId; //GPU ID USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. }ATOM_DISPLAY_OBJECT_PATH; typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH { - USHORT usDeviceTag; //supported device + USHORT usDeviceTag; //supported device USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH - USHORT usConnObjectId; //Connector Object ID - USHORT usGPUObjectId; //GPU ID - USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder + USHORT usConnObjectId; //Connector Object ID + USHORT usGPUObjectId; //GPU ID + USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE @@ -4041,7 +4041,7 @@ typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE }ATOM_DISPLAY_OBJECT_PATH_TABLE; -typedef struct _ATOM_OBJECT //each object has this structure +typedef struct _ATOM_OBJECT //each object has this structure { USHORT usObjectID; USHORT usSrcDstTableOffset; @@ -4049,7 +4049,7 @@ typedef struct _ATOM_OBJECT //each object has thi USHORT usReserved; }ATOM_OBJECT; -typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure +typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure { UCHAR ucNumberOfObjects; UCHAR ucPadding[3]; @@ -4088,7 +4088,7 @@ typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) //ucChannelMapping are defined as following -//for DP connector, eDP, DP to VGA/LVDS +//for DP connector, eDP, DP to VGA/LVDS //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 @@ -4108,7 +4108,7 @@ typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING #endif }ATOM_DP_CONN_CHANNEL_MAPPING; -//for DVI/HDMI, in dual link case, both links have to have same mapping. +//for DVI/HDMI, in dual link case, both links have to have same mapping. //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 @@ -4130,8 +4130,8 @@ typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING typedef struct _EXT_DISPLAY_PATH { - USHORT usDeviceTag; //A bit vector to show what devices are supported - USHORT usDeviceACPIEnum; //16bit device ACPI id. + USHORT usDeviceTag; //A bit vector to show what devices are supported + USHORT usDeviceACPIEnum; //16bit device ACPI id. USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT @@ -4143,9 +4143,9 @@ typedef struct _EXT_DISPLAY_PATH }; UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted USHORT usCaps; - USHORT usReserved; + USHORT usReserved; }EXT_DISPLAY_PATH; - + #define NUMBER_OF_UCHAR_FOR_GUID 16 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 @@ -4158,7 +4158,7 @@ typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. - UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. + UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. UCHAR uc3DStereoPinId; // use for eDP panel UCHAR ucRemoteDisplayConfig; UCHAR uceDPToLVDSRxId; @@ -4174,7 +4174,7 @@ typedef struct _ATOM_COMMON_RECORD_HEADER }ATOM_COMMON_RECORD_HEADER; -#define ATOM_I2C_RECORD_TYPE 1 +#define ATOM_I2C_RECORD_TYPE 1 #define ATOM_HPD_INT_RECORD_TYPE 2 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 @@ -4202,19 +4202,19 @@ typedef struct _ATOM_COMMON_RECORD_HEADER typedef struct _ATOM_I2C_RECORD { ATOM_COMMON_RECORD_HEADER sheader; - ATOM_I2C_ID_CONFIG sucI2cId; + ATOM_I2C_ID_CONFIG sucI2cId; UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC }ATOM_I2C_RECORD; typedef struct _ATOM_HPD_INT_RECORD { ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info UCHAR ucPlugged_PinState; }ATOM_HPD_INT_RECORD; -typedef struct _ATOM_OUTPUT_PROTECTION_RECORD +typedef struct _ATOM_OUTPUT_PROTECTION_RECORD { ATOM_COMMON_RECORD_HEADER sheader; UCHAR ucProtectionFlag; @@ -4262,7 +4262,7 @@ typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD { ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info + UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; @@ -4296,18 +4296,18 @@ typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins }ATOM_OBJECT_GPIO_CNTL_RECORD; -//Definitions for GPIO pin state +//Definitions for GPIO pin state #define GPIO_PIN_TYPE_INPUT 0x00 #define GPIO_PIN_TYPE_OUTPUT 0x10 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 -//For GPIO_PIN_TYPE_OUTPUT the following is defined +//For GPIO_PIN_TYPE_OUTPUT the following is defined #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 -// Indexes to GPIO array in GLSync record +// Indexes to GPIO array in GLSync record // GLSync record is for Frame Lock/Gen Lock feature. #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 @@ -4329,26 +4329,26 @@ typedef struct _ATOM_ENCODER_DVO_CF_RECORD // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder -#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled +#define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled typedef struct _ATOM_ENCODER_CAP_RECORD { ATOM_COMMON_RECORD_HEADER sheader; union { - USHORT usEncoderCap; + USHORT usEncoderCap; struct { #if ATOM_BIG_ENDIAN USHORT usReserved:14; // Bit1-15 may be defined for other capability in future USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable - USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. + USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. #else - USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. + USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable USHORT usReserved:14; // Bit1-15 may be defined for other capability in future #endif }; - }; -}ATOM_ENCODER_CAP_RECORD; + }; +}ATOM_ENCODER_CAP_RECORD; // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 @@ -4380,7 +4380,7 @@ typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; + ATOM_COMMON_RECORD_HEADER sheader; UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state UCHAR ucMuxControlPin; UCHAR ucMuxState[2]; //for alligment purpose @@ -4388,7 +4388,7 @@ typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD { - ATOM_COMMON_RECORD_HEADER sheader; + ATOM_COMMON_RECORD_HEADER sheader; UCHAR ucMuxType; UCHAR ucMuxControlPin; UCHAR ucMuxState[2]; //for alligment purpose @@ -4401,7 +4401,7 @@ typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE { ATOM_COMMON_RECORD_HEADER sheader; - UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table + UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE @@ -4447,9 +4447,9 @@ typedef struct _ATOM_BRACKET_LAYOUT_RECORD ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; }ATOM_BRACKET_LAYOUT_RECORD; -/****************************************************************************/ +/****************************************************************************/ // ASIC voltage data table -/****************************************************************************/ +/****************************************************************************/ typedef struct _ATOM_VOLTAGE_INFO_HEADER { USHORT usVDDCBaseLevel; //In number of 50mv unit @@ -4465,7 +4465,7 @@ typedef struct _ATOM_VOLTAGE_INFO_HEADER typedef struct _ATOM_VOLTAGE_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_VOLTAGE_INFO_HEADER viHeader; UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry }ATOM_VOLTAGE_INFO; @@ -4497,10 +4497,10 @@ typedef struct _ATOM_VOLTAGE_FORMULA_V2 typedef struct _ATOM_VOLTAGE_CONTROL { - UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine + UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine UCHAR ucVoltageControlI2cLine; UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; + UCHAR ucVoltageControlOffset; USHORT usGpioPin_AIndex; //GPIO_PAD register index UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff UCHAR ucReserved; @@ -4513,11 +4513,11 @@ typedef struct _ATOM_VOLTAGE_CONTROL #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage -#define VOLTAGE_CONTROL_ID_DS4402 0x04 -#define VOLTAGE_CONTROL_ID_UP6266 0x05 +#define VOLTAGE_CONTROL_ID_DS4402 0x04 +#define VOLTAGE_CONTROL_ID_UP6266 0x05 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 -#define VOLTAGE_CONTROL_ID_VT1556M 0x07 -#define VOLTAGE_CONTROL_ID_CHL822x 0x08 +#define VOLTAGE_CONTROL_ID_VT1556M 0x07 +#define VOLTAGE_CONTROL_ID_CHL822x 0x08 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 #define VOLTAGE_CONTROL_ID_UP1637 0x0A #define VOLTAGE_CONTROL_ID_CHL8214 0x0B @@ -4530,30 +4530,30 @@ typedef struct _ATOM_VOLTAGE_CONTROL typedef struct _ATOM_VOLTAGE_OBJECT { - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucSize; //Size of Object - ATOM_VOLTAGE_CONTROL asControl; //describ how to control - ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID }ATOM_VOLTAGE_OBJECT; typedef struct _ATOM_VOLTAGE_OBJECT_V2 { - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucSize; //Size of Object - ATOM_VOLTAGE_CONTROL asControl; //describ how to control - ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucSize; //Size of Object + ATOM_VOLTAGE_CONTROL asControl; //describ how to control + ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID }ATOM_VOLTAGE_OBJECT_V2; typedef struct _ATOM_VOLTAGE_OBJECT_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control }ATOM_VOLTAGE_OBJECT_INFO; typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control }ATOM_VOLTAGE_OBJECT_INFO_V2; typedef struct _ATOM_LEAKID_VOLTAGE @@ -4564,9 +4564,9 @@ typedef struct _ATOM_LEAKID_VOLTAGE }ATOM_LEAKID_VOLTAGE; typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ - UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI - UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase - USHORT usSize; //Size of Object + UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI + UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase + USHORT usSize; //Size of Object }ATOM_VOLTAGE_OBJECT_HEADER_V3; // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode @@ -4574,7 +4574,7 @@ typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 -#define VOLTAGE_OBJ_EVV 8 +#define VOLTAGE_OBJ_EVV 8 #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 @@ -4588,7 +4588,7 @@ typedef struct _VOLTAGE_LUT_ENTRY_V2 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 { USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register - USHORT usVoltageId; + USHORT usVoltageId; USHORT usLeakageId; // The corresponding Voltage Value, in mV }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; @@ -4598,7 +4598,7 @@ typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id UCHAR ucVoltageControlI2cLine; UCHAR ucVoltageControlAddress; - UCHAR ucVoltageControlOffset; + UCHAR ucVoltageControlOffset; ULONG ulReserved; VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff }ATOM_I2C_VOLTAGE_OBJECT_V3; @@ -4610,12 +4610,12 @@ typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 { ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT - UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode + UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table UCHAR ucPhaseDelay; // phase delay in unit of micro second - UCHAR ucReserved; + UCHAR ucReserved; ULONG ulGpioMaskVal; // GPIO Mask value - VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; + VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; }ATOM_GPIO_VOLTAGE_OBJECT_V3; typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 @@ -4623,9 +4623,9 @@ typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 UCHAR ucLeakageCntlId; // default is 0 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table - UCHAR ucReserved[2]; + UCHAR ucReserved[2]; ULONG ulMaxVoltageLevel; - LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; + LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; @@ -4635,9 +4635,9 @@ typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 // 14:7 PSI0_VID // 6 PSI0_EN // 5 PSI1 -// 4:2 load line slope trim. -// 1:0 offset trim, - USHORT usLoadLine_PSI; +// 4:2 load line slope trim. +// 1:0 offset trim, + USHORT usLoadLine_PSI; // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 @@ -4653,8 +4653,8 @@ typedef union _ATOM_VOLTAGE_OBJECT_V3{ typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control }ATOM_VOLTAGE_OBJECT_INFO_V3_1; typedef struct _ATOM_ASIC_PROFILE_VOLTAGE @@ -4663,28 +4663,28 @@ typedef struct _ATOM_ASIC_PROFILE_VOLTAGE UCHAR ucReserved; USHORT usSize; USHORT usEfuseSpareStartAddr; - USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, + USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage }ATOM_ASIC_PROFILE_VOLTAGE; //ucProfileId -#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 +#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 typedef struct _ATOM_ASIC_PROFILING_INFO { - ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_COMMON_TABLE_HEADER asHeader; ATOM_ASIC_PROFILE_VOLTAGE asVoltage; }ATOM_ASIC_PROFILING_INFO; typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 { - ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_COMMON_TABLE_HEADER asHeader; UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table - USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) + USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) - UCHAR ucElbVDDC_Num; + UCHAR ucElbVDDC_Num; USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array @@ -4695,7 +4695,7 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 { - ATOM_COMMON_TABLE_HEADER asHeader; + ATOM_COMMON_TABLE_HEADER asHeader; ULONG ulEvvDerateTdp; ULONG ulEvvDerateTdc; ULONG ulBoardCoreTemp; @@ -4745,7 +4745,7 @@ typedef struct _ATOM_POWER_SOURCE_OBJECT UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect UCHAR ucPwrSensActiveState; // high active or low active - UCHAR ucReserve[3]; // reserve + UCHAR ucReserve[3]; // reserve USHORT usSensPwr; // in unit of watt }ATOM_POWER_SOURCE_OBJECT; @@ -4771,15 +4771,15 @@ typedef struct _ATOM_POWER_SOURCE_INFO typedef struct _ATOM_CLK_VOLT_CAPABILITY { - ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table + ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz }ATOM_CLK_VOLT_CAPABILITY; typedef struct _ATOM_AVAILABLE_SCLK_LIST { ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz - USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK - USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK + USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK + USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK }ATOM_AVAILABLE_SCLK_LIST; // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition @@ -4790,28 +4790,28 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 { ATOM_COMMON_TABLE_HEADER sHeader; ULONG ulBootUpEngineClock; - ULONG ulDentistVCOFreq; - ULONG ulBootUpUMAClock; - ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; + ULONG ulDentistVCOFreq; + ULONG ulBootUpUMAClock; + ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ULONG ulBootUpReqDisplayVector; ULONG ulOtherDisplayMisc; ULONG ulGPUCapInfo; ULONG ulSB_MMIO_Base_Addr; USHORT usRequestedPWMFreqInHz; - UCHAR ucHtcTmpLmt; + UCHAR ucHtcTmpLmt; UCHAR ucHtcHystLmt; - ULONG ulMinEngineClock; - ULONG ulSystemConfig; - ULONG ulCPUCapInfo; - USHORT usNBP0Voltage; + ULONG ulMinEngineClock; + ULONG ulSystemConfig; + ULONG ulCPUCapInfo; + USHORT usNBP0Voltage; USHORT usNBP1Voltage; - USHORT usBootUpNBVoltage; + USHORT usBootUpNBVoltage; USHORT usExtDispConnInfoOffset; - USHORT usPanelRefreshRateRange; - UCHAR ucMemoryType; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; UCHAR ucUMAChannelNumber; - ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; - ULONG ulCSR_M3_ARB_CNTL_UVD[10]; + ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; + ULONG ulCSR_M3_ARB_CNTL_UVD[10]; ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ULONG ulGMCRestoreResetTime; @@ -4829,24 +4829,24 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 USHORT usDVISSpreadRateIn10Hz; ULONG SclkDpmBoostMargin; ULONG SclkDpmThrottleMargin; - USHORT SclkDpmTdpLimitPG; + USHORT SclkDpmTdpLimitPG; USHORT SclkDpmTdpLimitBoost; ULONG ulBoostEngineCLock; - UCHAR ulBoostVid_2bit; + UCHAR ulBoostVid_2bit; UCHAR EnableBoost; USHORT GnbTdpLimit; USHORT usMaxLVDSPclkFreqInSingleLink; UCHAR ucLvdsMisc; UCHAR ucLVDSReserved; - ULONG ulReserved3[15]; - ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; -}ATOM_INTEGRATED_SYSTEM_INFO_V6; + ULONG ulReserved3[15]; + ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; +}ATOM_INTEGRATED_SYSTEM_INFO_V6; // ulGPUCapInfo #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 -//ucLVDSMisc: +//ucLVDSMisc: #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 #define SYS_INFO_LVDSMISC__888_BPC 0x04 @@ -4862,57 +4862,57 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V6 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock -ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. -ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement. - + ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_CRT2_SUPPORT 0x0010 - ATOM_DEVICE_DFP1_SUPPORT 0x0008 - ATOM_DEVICE_DFP6_SUPPORT 0x0040 - ATOM_DEVICE_DFP2_SUPPORT 0x0080 - ATOM_DEVICE_DFP3_SUPPORT 0x0200 - ATOM_DEVICE_DFP4_SUPPORT 0x0400 + ATOM_DEVICE_DFP1_SUPPORT 0x0008 + ATOM_DEVICE_DFP6_SUPPORT 0x0040 + ATOM_DEVICE_DFP2_SUPPORT 0x0080 + ATOM_DEVICE_DFP3_SUPPORT 0x0200 + ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 -ulOtherDisplayMisc: Other display related flags, not defined yet. +ulOtherDisplayMisc: Other display related flags, not defined yet. ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. =1: TMDS/HDMI Coherent Mode use signel PLL mode. bit[3]=0: Enable HW AUX mode detection logic =1: Disable HW AUX mode dettion logic ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. -usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; - + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, - Changing BL using VBIOS function is functional in both driver and non-driver present environment; + Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but - it's per platform + it's per platform and enabling VariBri under the driver environment from PP table is optional. -ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. +ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. -ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. -ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. - 1: DDR-PLL Power down feature enabled. + 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State -usNBP1Voltage: VID for voltage on NB P1 State +usNBP1Voltage: VID for voltage on NB P1 State usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set @@ -4922,24 +4922,24 @@ usPanelRefreshRateRange: Bit vector for LCD supported refresh rate rang SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. -ucUMAChannelNumber: System memory channel numbers. +ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. -sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high -ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. -ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. +sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. -usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. -usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped @@ -4951,9 +4951,9 @@ ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 pan // this Table is used for Liano/Ontario APU typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 { - ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; - ULONG ulPowerplayTable[128]; -}ATOM_FUSION_SYSTEM_INFO_V1; + ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; + ULONG ulPowerplayTable[128]; +}ATOM_FUSION_SYSTEM_INFO_V1; typedef struct _ATOM_TDP_CONFIG_BITS @@ -4980,8 +4980,8 @@ typedef union _ATOM_TDP_CONFIG /********************************************************************************************************************** ATOM_FUSION_SYSTEM_INFO_V1 Description sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. -ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] -**********************************************************************************************************************/ +ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] +**********************************************************************************************************************/ // this IntegrateSystemInfoTable is used for Trinity APU typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 @@ -4999,14 +4999,14 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 UCHAR ucHtcTmpLmt; UCHAR ucHtcHystLmt; ULONG ulMinEngineClock; - ULONG ulSystemConfig; + ULONG ulSystemConfig; ULONG ulCPUCapInfo; - USHORT usNBP0Voltage; + USHORT usNBP0Voltage; USHORT usNBP1Voltage; - USHORT usBootUpNBVoltage; + USHORT usBootUpNBVoltage; USHORT usExtDispConnInfoOffset; - USHORT usPanelRefreshRateRange; - UCHAR ucMemoryType; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; UCHAR ucUMAChannelNumber; UCHAR strVBIOSMsg[40]; ATOM_TDP_CONFIG asTdpConfig; @@ -5027,10 +5027,10 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 USHORT usDVISSpreadRateIn10Hz; ULONG SclkDpmBoostMargin; ULONG SclkDpmThrottleMargin; - USHORT SclkDpmTdpLimitPG; + USHORT SclkDpmTdpLimitPG; USHORT SclkDpmTdpLimitBoost; ULONG ulBoostEngineCLock; - UCHAR ulBoostVid_2bit; + UCHAR ulBoostVid_2bit; UCHAR EnableBoost; USHORT GnbTdpLimit; USHORT usMaxLVDSPclkFreqInSingleLink; @@ -5046,7 +5046,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 UCHAR ucMinAllowedBL_Level; ULONG ulLCDBitDepthControlVal; ULONG ulNbpStateMemclkFreq[4]; - USHORT usNBP2Voltage; + USHORT usNBP2Voltage; USHORT usNBP3Voltage; ULONG ulNbpStateNClkFreq[4]; UCHAR ucNBDPMEnable; @@ -5077,21 +5077,21 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock -ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. -ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement. - + ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 - ATOM_DEVICE_DFP1_SUPPORT 0x0008 - ATOM_DEVICE_DFP6_SUPPORT 0x0040 - ATOM_DEVICE_DFP2_SUPPORT 0x0080 - ATOM_DEVICE_DFP3_SUPPORT 0x0200 - ATOM_DEVICE_DFP4_SUPPORT 0x0400 + ATOM_DEVICE_DFP1_SUPPORT 0x0008 + ATOM_DEVICE_DFP6_SUPPORT 0x0040 + ATOM_DEVICE_DFP2_SUPPORT 0x0080 + ATOM_DEVICE_DFP3_SUPPORT 0x0200 + ATOM_DEVICE_DFP4_SUPPORT 0x0400 ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 -ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. - =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. +ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. + =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS @@ -5104,41 +5104,41 @@ ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade =1: DP mode use single PLL mode bit[3]=0: Enable AUX HW mode detection logic =1: Disable AUX HW mode detection logic - + ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. -usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; - + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, - Changing BL using VBIOS function is functional in both driver and non-driver present environment; + Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but - it's per platform + it's per platform and enabling VariBri under the driver environment from PP table is optional. -ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. +ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. -ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. -ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. - 1: DDR-PLL Power down feature enabled. + 1: DDR-PLL Power down feature enabled. ulCPUCapInfo: TBD usNBP0Voltage: VID for voltage on NB P0 State -usNBP1Voltage: VID for voltage on NB P1 State +usNBP1Voltage: VID for voltage on NB P1 State usNBP2Voltage: VID for voltage on NB P2 State -usNBP3Voltage: VID for voltage on NB P3 State +usNBP3Voltage: VID for voltage on NB P3 State usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set @@ -5148,24 +5148,24 @@ usPanelRefreshRateRange: Bit vector for LCD supported refresh rate rang SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. -ucUMAChannelNumber: System memory channel numbers. +ucUMAChannelNumber: System memory channel numbers. ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. -sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high -ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. -ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. +sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. -usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. -usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped @@ -5173,40 +5173,40 @@ ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 pan [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 -ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust +ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). - =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. + =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). - =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. +ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). + =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. +ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. +ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. +ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. =0 means to use VBIOS default delay which is 125 ( 500ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: - LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. + LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: - LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. +ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. +ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. -ulNbpStateMemclkFreq[4]: system memory clock frequency in unit of 10Khz in different NB pstate. +ulNbpStateMemclkFreq[4]: system memory clock frequency in unit of 10Khz in different NB pstate. **********************************************************************************************************************/ @@ -5226,13 +5226,13 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 UCHAR ucHtcTmpLmt; UCHAR ucHtcHystLmt; ULONG ulReserved2; - ULONG ulSystemConfig; + ULONG ulSystemConfig; ULONG ulCPUCapInfo; ULONG ulReserved3; USHORT usGPUReservedSysMemSize; USHORT usExtDispConnInfoOffset; - USHORT usPanelRefreshRateRange; - UCHAR ucMemoryType; + USHORT usPanelRefreshRateRange; + UCHAR ucMemoryType; UCHAR ucUMAChannelNumber; UCHAR strVBIOSMsg[40]; ATOM_TDP_CONFIG asTdpConfig; @@ -5267,21 +5267,21 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 UCHAR ucMinAllowedBL_Level; ULONG ulLCDBitDepthControlVal; ULONG ulNbpStateMemclkFreq[4]; - ULONG ulReserved6; + ULONG ulReserved6; ULONG ulNbpStateNClkFreq[4]; - USHORT usNBPStateVoltage[4]; - USHORT usBootUpNBVoltage; - USHORT usReserved2; + USHORT usNBPStateVoltage[4]; + USHORT usBootUpNBVoltage; + USHORT usReserved2; ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; }ATOM_INTEGRATED_SYSTEM_INFO_V1_8; /********************************************************************************************************************** ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock -ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. -ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. +ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. +ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). - + ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_DFP1_SUPPORT 0x0008 @@ -5292,8 +5292,8 @@ ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are suppo ATOM_DEVICE_DFP5_SUPPORT 0x0800 ATOM_DEVICE_LCD1_SUPPORT 0x0002 -ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface - bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. +ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface + bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS @@ -5308,34 +5308,34 @@ ulGPUCapInfo: bit[0~2]= Reserved bit[4]=0: Disable DFS bypass feature =1: Enable DFS bypass feature -usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). +usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; - + When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, - Changing BL using VBIOS function is functional in both driver and non-driver present environment; + Changing BL using VBIOS function is functional in both driver and non-driver present environment; and enabling VariBri under the driver environment from PP table is optional. 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating that BL control from GPU is expected. VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but - it's per platform + it's per platform and enabling VariBri under the driver environment from PP table is optional. ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. -ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. +ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. -ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled +ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled =1: PCIE Power Gating Enabled Bit[1]=0: DDR-DLL shut-down feature disabled. 1: DDR-DLL shut-down feature enabled. Bit[2]=0: DDR-PLL Power down feature disabled. - 1: DDR-PLL Power down feature enabled. + 1: DDR-PLL Power down feature enabled. Bit[3]=0: GNB DPM is disabled - =1: GNB DPM is enabled + =1: GNB DPM is enabled ulCPUCapInfo: TBD usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure @@ -5347,29 +5347,29 @@ usPanelRefreshRateRange: Bit vector for LCD supported refresh rate rang SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. -ucUMAChannelNumber: System memory channel numbers. +ucUMAChannelNumber: System memory channel numbers. -strVBIOSMsg[40]: VBIOS boot up customized message string +strVBIOSMsg[40]: VBIOS boot up customized message string -sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high +sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high -ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. +ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. -usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. -usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. -usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. -usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. +usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. +usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. +usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. -ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. -ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. +ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. +ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode @@ -5378,45 +5378,45 @@ ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 pan [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 -ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust +ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust value to program Travis register LVDS_CTRL_4 -ucLVDSPwrOnSeqDIGONtoDE_in4Ms: +ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). - =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. + =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOnDEtoVARY_BL_in4Ms: - LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). - =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. +ucLVDSPwrOnDEtoVARY_BL_in4Ms: + LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). + =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffVARY_BLtoDE_in4Ms: - LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. +ucLVDSPwrOffVARY_BLtoDE_in4Ms: + LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffDEtoDIGON_in4Ms: - LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. +ucLVDSPwrOffDEtoDIGON_in4Ms: + LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSOffToOnDelay_in4Ms: - LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. +ucLVDSOffToOnDelay_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. =0 means to use VBIOS default delay which is 125 ( 500ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: - LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. + LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: - LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. +ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: + LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. =0 means to use VBIOS default delay which is 0 ( 0ms ). This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. -ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. +ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL ulNbpStateMemclkFreq[4]: system memory clock frequency in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage -usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded +usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded sExtDispConnInfo: Display connector information table provided to VBIOS **********************************************************************************************************************/ @@ -5426,7 +5426,7 @@ typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 { ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure -}ATOM_FUSION_SYSTEM_INFO_V2; +}ATOM_FUSION_SYSTEM_INFO_V2; /**************************************************************************/ @@ -5451,13 +5451,13 @@ typedef struct _ATOM_I2C_DEVICE_SETUP_INFO UCHAR ucSSChipID; //SS chip being used UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip UCHAR ucNumOfI2CDataRecords; //number of data block - ATOM_I2C_DATA_RECORD asI2CData[1]; + ATOM_I2C_DATA_RECORD asI2CData[1]; }ATOM_I2C_DEVICE_SETUP_INFO; //========================================================================================== typedef struct _ATOM_ASIC_MVDD_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; }ATOM_ASIC_MVDD_INFO; @@ -5513,14 +5513,14 @@ typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; }ATOM_ASIC_INTERNAL_SS_INFO; typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. }ATOM_ASIC_INTERNAL_SS_INFO_V2; typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 @@ -5541,8 +5541,8 @@ typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 { - ATOM_COMMON_TABLE_HEADER sHeader; - ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. + ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. }ATOM_ASIC_INTERNAL_SS_INFO_V3; @@ -5559,7 +5559,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 #define ATOM_INTERNAL_TIMER_DEF 10 -// BIOS_0_SCRATCH Definition +// BIOS_0_SCRATCH Definition #define ATOM_S0_CRT1_MONO 0x00000001L #define ATOM_S0_CRT1_COLOR 0x00000002L #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) @@ -5597,14 +5597,14 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 -#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with +#define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L #define ATOM_S0_THERMAL_STATE_SHIFT 26 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L -#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 +#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 @@ -5853,11 +5853,11 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define ATOM_S6_LID_STATEb0 0x40 #define ATOM_S6_DOCK_STATEb0 0x80 #define ATOM_S6_CRITICAL_STATEb1 0x01 -#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 +#define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 -#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 -#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 +#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 +#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 @@ -5915,26 +5915,26 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 // BIOS_8_SCRATCH Definition #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF -#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 +#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 // BIOS_9_SCRATCH Definition -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF #endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 #endif -#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT +#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 #endif -#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT +#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 #endif - + #define ATOM_FLAG_SET 0x20 #define ATOM_FLAG_CLEAR 0 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) @@ -5957,7 +5957,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) -#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) +#define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) @@ -5972,7 +5972,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) -/****************************************************************************/ +/****************************************************************************/ //Portion II: Definitinos only used in Driver /****************************************************************************/ @@ -5992,7 +5992,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION -/****************************************************************************/ +/****************************************************************************/ //Portion III: Definitinos only used in VBIOS /****************************************************************************/ #define ATOM_DAC_SRC 0x80 @@ -6011,13 +6011,13 @@ typedef struct _MEMORY_PLLINIT_PARAMETERS #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS -#define GPIO_PIN_WRITE 0x01 +#define GPIO_PIN_WRITE 0x01 #define GPIO_PIN_READ 0x00 typedef struct _GPIO_PIN_CONTROL_PARAMETERS { UCHAR ucGPIO_ID; //return value, read from GPIO pins - UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update + UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write }GPIO_PIN_CONTROL_PARAMETERS; @@ -6026,10 +6026,10 @@ typedef struct _ENABLE_SCALER_PARAMETERS { UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION - UCHAR ucTVStandard; // + UCHAR ucTVStandard; // UCHAR ucPadding[1]; -}ENABLE_SCALER_PARAMETERS; -#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS +}ENABLE_SCALER_PARAMETERS; +#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS //ucEnable: #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 @@ -6049,14 +6049,14 @@ typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION { ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; - ENABLE_CRTC_PARAMETERS sReserved; + ENABLE_CRTC_PARAMETERS sReserved; }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS { USHORT usHight; // Image Hight USHORT usWidth; // Image Width - UCHAR ucSurface; // Surface 1 or 2 + UCHAR ucSurface; // Surface 1 or 2 UCHAR ucPadding[3]; }ENABLE_GRAPH_SURFACE_PARAMETERS; @@ -6075,7 +6075,7 @@ typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 USHORT usWidth; // Image Width UCHAR ucSurface; // Surface 1 or 2 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE - USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. + USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 @@ -6097,7 +6097,7 @@ typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION { - ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; + ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; @@ -6110,23 +6110,23 @@ typedef struct _MEMORY_CLEAN_UP_PARAMETERS typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS { - USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC + USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC USHORT usY_Size; -}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; +}GET_DISPLAY_SURFACE_SIZE_PARAMETERS; typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 { union{ - USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC - USHORT usSurface; + USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC + USHORT usSurface; }; USHORT usY_Size; - USHORT usDispXStart; + USHORT usDispXStart; USHORT usDispYStart; -}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; +}GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; -typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 +typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 { UCHAR ucLutId; UCHAR ucAction; @@ -6156,7 +6156,7 @@ typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 #define HDP4_INTERRUPT_ID 4 #define HDP5_INTERRUPT_ID 5 #define HDP6_INTERRUPT_ID 6 -#define SW_INTERRUPT_ID 11 +#define SW_INTERRUPT_ID 11 // ucAction #define INTERRUPT_SERVICE_GEN_SW_INT 1 @@ -6168,7 +6168,7 @@ typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 typedef struct _INDIRECT_IO_ACCESS { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR IOAccessSequence[256]; } INDIRECT_IO_ACCESS; @@ -6197,7 +6197,7 @@ typedef struct _INDIRECT_IO_ACCESS #define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE typedef struct _ATOM_OEM_INFO -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; }ATOM_OEM_INFO; @@ -6210,12 +6210,12 @@ typedef struct _ATOM_TV_MODE typedef struct _ATOM_BIOS_INT_TVSTD_MODE { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table - USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table - USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table + USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table + USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table }ATOM_BIOS_INT_TVSTD_MODE; @@ -6228,13 +6228,13 @@ typedef struct _ATOM_TV_MODE_SCALER_PTR typedef struct _ATOM_STANDARD_VESA_TIMING { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation }ATOM_STANDARD_VESA_TIMING; typedef struct _ATOM_STD_FORMAT -{ +{ USHORT usSTD_HDisp; USHORT usSTD_VDisp; USHORT usSTD_RefreshRate; @@ -6248,8 +6248,8 @@ typedef struct _ATOM_VESA_TO_EXTENDED_MODE }ATOM_VESA_TO_EXTENDED_MODE; typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT -{ - ATOM_COMMON_TABLE_HEADER sHeader; +{ + ATOM_COMMON_TABLE_HEADER sHeader; ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; }ATOM_VESA_TO_INTENAL_MODE_LUT; @@ -6315,7 +6315,7 @@ typedef struct _ATOM_INIT_REG_BLOCK{ #define ACCESS_PLACEHOLDER 0x80 typedef struct _ATOM_MC_INIT_PARAM_TABLE -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usAdjustARB_SEQDataOffset; USHORT usMCInitMemTypeTblOffset; @@ -6391,12 +6391,12 @@ typedef struct _MCuCodeHeader typedef struct _ATOM_VRAM_MODULE_V1 { ULONG ulReserved; - USHORT usEMRSValue; + USHORT usEMRSValue; USHORT usMRSValue; USHORT usReserved; UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; - UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender + UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... UCHAR ucRow; // Number of Row,in power of 2; UCHAR ucColumn; // Number of Column,in power of 2; @@ -6418,7 +6418,7 @@ typedef struct _ATOM_VRAM_MODULE_V2 ULONG ulMemoryClock; // Override of default memory clock for particular memory type USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type - USHORT usEMRSValue; + USHORT usEMRSValue; USHORT usMRSValue; USHORT usReserved; UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module @@ -6440,9 +6440,9 @@ typedef struct _ATOM_VRAM_MODULE_V2 typedef struct _ATOM_MEMORY_TIMING_FORMAT { - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing union{ - USHORT usMRS; // mode register + USHORT usMRS; // mode register USHORT usDDR3_MR0; }; union{ @@ -6450,24 +6450,24 @@ typedef struct _ATOM_MEMORY_TIMING_FORMAT USHORT usDDR3_MR1; }; UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency + UCHAR ucWL; // WRITE Latency UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC + UCHAR uctRC; // tRC UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR + UCHAR uctRCDR; // tRCDR UCHAR uctRCDW; // tRCDW UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD + UCHAR uctRRD; // tRRD UCHAR uctWR; // tWR UCHAR uctWTR; // tWTR UCHAR uctPDIX; // tPDIX UCHAR uctFAW; // tFAW UCHAR uctAOND; // tAOND - union + union { struct { - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon - UCHAR ucReserved; + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucReserved; }; USHORT usDDR3_MR2; }; @@ -6476,71 +6476,71 @@ typedef struct _ATOM_MEMORY_TIMING_FORMAT typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 { - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing - USHORT usMRS; // mode register + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register USHORT usEMRS; // extended mode register UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency + UCHAR ucWL; // WRITE Latency UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC + UCHAR uctRC; // tRC UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR + UCHAR uctRCDR; // tRCDR UCHAR uctRCDW; // tRCDW UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD + UCHAR uctRRD; // tRRD UCHAR uctWR; // tWR UCHAR uctWTR; // tWTR UCHAR uctPDIX; // tPDIX UCHAR uctFAW; // tFAW UCHAR uctAOND; // tAOND - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon ////////////////////////////////////GDDR parameters/////////////////////////////////// - UCHAR uctCCDL; // - UCHAR uctCRCRL; // - UCHAR uctCRCWL; // - UCHAR uctCKE; // - UCHAR uctCKRSE; // - UCHAR uctCKRSX; // - UCHAR uctFAW32; // - UCHAR ucMR5lo; // - UCHAR ucMR5hi; // + UCHAR uctCCDL; // + UCHAR uctCRCRL; // + UCHAR uctCRCWL; // + UCHAR uctCKE; // + UCHAR uctCKRSE; // + UCHAR uctCKRSX; // + UCHAR uctFAW32; // + UCHAR ucMR5lo; // + UCHAR ucMR5hi; // UCHAR ucTerminator; }ATOM_MEMORY_TIMING_FORMAT_V1; typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 { - ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing - USHORT usMRS; // mode register + ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing + USHORT usMRS; // mode register USHORT usEMRS; // extended mode register UCHAR ucCL; // CAS latency - UCHAR ucWL; // WRITE Latency + UCHAR ucWL; // WRITE Latency UCHAR uctRAS; // tRAS - UCHAR uctRC; // tRC + UCHAR uctRC; // tRC UCHAR uctRFC; // tRFC - UCHAR uctRCDR; // tRCDR + UCHAR uctRCDR; // tRCDR UCHAR uctRCDW; // tRCDW UCHAR uctRP; // tRP - UCHAR uctRRD; // tRRD + UCHAR uctRRD; // tRRD UCHAR uctWR; // tWR UCHAR uctWTR; // tWTR UCHAR uctPDIX; // tPDIX UCHAR uctFAW; // tFAW UCHAR uctAOND; // tAOND - UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon + UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon ////////////////////////////////////GDDR parameters/////////////////////////////////// - UCHAR uctCCDL; // - UCHAR uctCRCRL; // - UCHAR uctCRCWL; // - UCHAR uctCKE; // - UCHAR uctCKRSE; // - UCHAR uctCKRSX; // - UCHAR uctFAW32; // - UCHAR ucMR4lo; // - UCHAR ucMR4hi; // - UCHAR ucMR5lo; // - UCHAR ucMR5hi; // + UCHAR uctCCDL; // + UCHAR uctCRCRL; // + UCHAR uctCRCWL; // + UCHAR uctCKE; // + UCHAR uctCKRSE; // + UCHAR uctCKRSX; // + UCHAR uctFAW32; // + UCHAR ucMR4lo; // + UCHAR ucMR4hi; // + UCHAR ucMR5lo; // + UCHAR ucMR5hi; // UCHAR ucTerminator; - UCHAR ucReserved; + UCHAR ucReserved; }ATOM_MEMORY_TIMING_FORMAT_V2; typedef struct _ATOM_MEMORY_FORMAT @@ -6562,7 +6562,7 @@ typedef struct _ATOM_MEMORY_FORMAT UCHAR ucRank; // Number of Rank, in power of 2 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) - UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms + UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc @@ -6578,7 +6578,7 @@ typedef struct _ATOM_VRAM_MODULE_V3 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module UCHAR ucChannelNum; // board dependent parameter:Number of channel; - UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit + UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters UCHAR ucFlag; // To enable/disable functionalities based on memory type @@ -6621,7 +6621,7 @@ typedef struct _ATOM_VRAM_MODULE_V4 union{ USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type USHORT usDDR3_MR3; // Used for DDR3 memory - }; + }; UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) UCHAR ucReserved2[2]; @@ -6717,13 +6717,13 @@ typedef struct _ATOM_VRAM_MODULE_V7 USHORT usSEQSettingOffset; UCHAR ucReserved; // Memory Module specific values - USHORT usEMRS2Value; // EMRS2/MR2 Value. + USHORT usEMRS2Value; // EMRS2/MR2 Value. USHORT usEMRS3Value; // EMRS3/MR3 Value. UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth - char strMemPNString[20]; // part number end with '0'. + char strMemPNString[20]; // part number end with '0'. }ATOM_VRAM_MODULE_V7; typedef struct _ATOM_VRAM_INFO_V2 @@ -6756,7 +6756,7 @@ typedef struct _ATOM_VRAM_INFO_V4 USHORT usRerseved; UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] - UCHAR ucReservde[4]; + UCHAR ucReservde[4]; UCHAR ucNumOfVRAMModule; ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; ATOM_INIT_REG_BLOCK asMemPatch; // for allocation @@ -6773,7 +6773,7 @@ typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version - UCHAR ucReserved; + UCHAR ucReserved; ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; }ATOM_VRAM_INFO_HEADER_V2_1; @@ -6797,18 +6797,18 @@ typedef struct _ATOM_MEMORY_TRAINING_INFO typedef struct SW_I2C_CNTL_DATA_PARAMETERS { UCHAR ucControl; - UCHAR ucData; - UCHAR ucSatus; - UCHAR ucTemp; + UCHAR ucData; + UCHAR ucSatus; + UCHAR ucTemp; } SW_I2C_CNTL_DATA_PARAMETERS; #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS typedef struct _SW_I2C_IO_DATA_PARAMETERS -{ +{ USHORT GPIO_Info; - UCHAR ucAct; - UCHAR ucData; + UCHAR ucAct; + UCHAR ucData; } SW_I2C_IO_DATA_PARAMETERS; #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS @@ -6842,8 +6842,8 @@ typedef struct _SW_I2C_IO_DATA_PARAMETERS typedef struct _PTR_32_BIT_STRUCTURE { - USHORT Offset16; - USHORT Segment16; + USHORT Offset16; + USHORT Segment16; } PTR_32_BIT_STRUCTURE; typedef union _PTR_32_BIT_UNION @@ -6963,7 +6963,7 @@ typedef struct _VESA_MODE_INFO_BLOCK #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 -#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B +#define ATOM_BIOS_FUNCTION_GET_DDC 0x0B #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F #define ATOM_BIOS_FUNCTION_STV_STD 0x16 @@ -6973,28 +6973,28 @@ typedef struct _VESA_MODE_INFO_BLOCK #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 -#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A +#define ATOM_BIOS_FUNCTION_HW_ICON 0x8A #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E -#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F -#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 +#define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F +#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported - -#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS -#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 -#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 -#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. -#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY + +#define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS +#define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 +#define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 +#define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. +#define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) @@ -7037,7 +7037,7 @@ typedef struct _ASIC_ENCODER_INFO typedef struct _ATOM_DISP_OUT_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT ptrTransmitterInfo; USHORT ptrEncoderInfo; ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; @@ -7046,17 +7046,17 @@ typedef struct _ATOM_DISP_OUT_INFO typedef struct _ATOM_DISP_OUT_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT ptrTransmitterInfo; USHORT ptrEncoderInfo; - USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. + USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; ASIC_ENCODER_INFO asEncoderInfo[1]; }ATOM_DISP_OUT_INFO_V2; typedef struct _ATOM_DISP_CLOCK_ID { - UCHAR ucPpllId; + UCHAR ucPpllId; UCHAR ucPpllAttribute; }ATOM_DISP_CLOCK_ID; @@ -7080,12 +7080,12 @@ typedef struct _ASIC_TRANSMITTER_INFO_V2 typedef struct _ATOM_DISP_OUT_INFO_V3 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT ptrTransmitterInfo; USHORT ptrEncoderInfo; - USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. + USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. USHORT usReserved; - UCHAR ucDCERevision; + UCHAR ucDCERevision; UCHAR ucMaxDispEngineNum; UCHAR ucMaxActiveDispEngineNum; UCHAR ucMaxPPLLNum; @@ -7108,7 +7108,7 @@ typedef enum CORE_REF_CLK_SOURCE{ // DispDevicePriorityInfo typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT asDevicePriority[16]; }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; @@ -7149,7 +7149,7 @@ typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 typedef struct _DP_ENCODER_SERVICE_PARAMETERS { USHORT ucLinkClock; - union + union { UCHAR ucConfig; // for DP training command UCHAR ucI2cId; // use for GET_SINK_TYPE command @@ -7187,7 +7187,7 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION UCHAR ucAuxId; UCHAR ucAction; - UCHAR ucSinkType; // Iput and Output parameters. + UCHAR ucSinkType; // Iput and Output parameters. UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION UCHAR ucReserved[2]; }DP_ENCODER_SERVICE_PARAMETERS_V2; @@ -7204,7 +7204,7 @@ typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 // DP_TRAINING_TABLE -#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR +#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) @@ -7215,7 +7215,7 @@ typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) -#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) +#define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS @@ -7227,7 +7227,7 @@ typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS UCHAR ucStatus; }; USHORT lpI2CDataOut; - UCHAR ucFlag; + UCHAR ucFlag; UCHAR ucTransBytes; UCHAR ucSlaveAddr; UCHAR ucLineNumber; @@ -7240,17 +7240,17 @@ typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS #define HW_I2C_READ 0 #define I2C_2BYTE_ADDR 0x02 -/****************************************************************************/ +/****************************************************************************/ // Structures used by HW_Misc_OperationTable -/****************************************************************************/ -typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 +/****************************************************************************/ +typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 { UCHAR ucCmd; // Input: To tell which action to take UCHAR ucReserved[3]; ULONG ulReserved; -}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; +}ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; -typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 +typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 { UCHAR ucReturnCode; // Output: Return value base on action was taken UCHAR ucReserved[3]; @@ -7260,7 +7260,7 @@ typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 // Actions code #define ATOM_GET_SDI_SUPPORT 0xF0 -// Return code +// Return code #define ATOM_UNKNOWN_CMD 0 #define ATOM_FEATURE_NOT_SUPPORTED 1 #define ATOM_FEATURE_SUPPORTED 2 @@ -7268,15 +7268,15 @@ typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION { ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; - PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; + PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; -/****************************************************************************/ +/****************************************************************************/ typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 { UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... - UCHAR ucReserved[3]; + UCHAR ucReserved[3]; }SET_HWBLOCK_INSTANCE_PARAMETER_V2; #define HWBLKINST_INSTANCE_MASK 0x07 @@ -7293,24 +7293,24 @@ typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 #define SELECT_CRTC_PIXEL_RATE 7 #define SELECT_VGA_BLK 8 -// DIGTransmitterInfoTable structure used to program UNIPHY settings -typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock - USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info +// DIGTransmitterInfoTable structure used to program UNIPHY settings +typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock + USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range - USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info + USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings }DIG_TRANSMITTER_INFO_HEADER_V3_1; -typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock - USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info +typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock + USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range - USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info + USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings - USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info + USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings }DIG_TRANSMITTER_INFO_HEADER_V3_2; @@ -7371,9 +7371,9 @@ typedef struct _PHY_ANALOG_SETTING_INFO_V2{ typedef struct _GFX_HAVESTING_PARAMETERS { UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM - UCHAR ucReserved; //reserved + UCHAR ucReserved; //reserved UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array - UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array + UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array } GFX_HAVESTING_PARAMETERS; //ucGfxBlkId @@ -7381,7 +7381,7 @@ typedef struct _GFX_HAVESTING_PARAMETERS { #define GFX_HARVESTING_RB_ID 1 #define GFX_HARVESTING_PRIM_ID 2 -/****************************************************************************/ +/****************************************************************************/ //Portion VI: Definitinos for vbios MC scratch registers that driver used /****************************************************************************/ @@ -7402,7 +7402,7 @@ typedef struct _GFX_HAVESTING_PARAMETERS { #define ATOM_MEM_TYPE_HBM_STRING "HBM" #define ATOM_MEM_TYPE_DDR3_STRING "DDR3" -/****************************************************************************/ +/****************************************************************************/ //Portion VI: Definitinos being oboselete /****************************************************************************/ @@ -7410,15 +7410,15 @@ typedef struct _GFX_HAVESTING_PARAMETERS { //Remove the definitions below when driver is ready! typedef struct _ATOM_DAC_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT usMaxFrequency; // in 10kHz unit USHORT usReserved; }ATOM_DAC_INFO; -typedef struct _COMPASSIONATE_DATA +typedef struct _COMPASSIONATE_DATA { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; //============================== DAC1 portion UCHAR ucDAC1_BG_Adjustment; @@ -7448,7 +7448,7 @@ typedef struct _COMPASSIONATE_DATA /****************************Supported Device Info Table Definitions**********************/ // ucConnectInfo: // [7:4] - connector type -// = 1 - VGA connector +// = 1 - VGA connector // = 2 - DVI-I // = 3 - DVI-D // = 4 - DVI-A @@ -7467,7 +7467,7 @@ typedef struct _COMPASSIONATE_DATA // = 2 - DACB // = 3 - External DAC // Others=TBD -// +// typedef struct _ATOM_CONNECTOR_INFO { @@ -7494,7 +7494,7 @@ typedef struct _ATOM_CONNECTOR_INFO_I2C typedef struct _ATOM_SUPPORTED_DEVICES_INFO -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; @@ -7508,7 +7508,7 @@ typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP }ATOM_CONNECTOR_INC_SRC_BITMAP; typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; @@ -7516,7 +7516,7 @@ typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 }ATOM_SUPPORTED_DEVICES_INFO_2; typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 -{ +{ ATOM_COMMON_TABLE_HEADER sHeader; USHORT usDeviceSupport; ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; @@ -7534,14 +7534,14 @@ typedef struct _ATOM_MISC_CONTROL_INFO UCHAR ucPLL_DutyCycle; // PLL duty cycle control UCHAR ucPLL_VCO_Gain; // PLL VCO gain control UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control -}ATOM_MISC_CONTROL_INFO; +}ATOM_MISC_CONTROL_INFO; #define ATOM_MAX_MISC_INFO 4 typedef struct _ATOM_TMDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; USHORT usMaxFrequency; // in 10Khz ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; }ATOM_TMDS_INFO; @@ -7549,14 +7549,14 @@ typedef struct _ATOM_TMDS_INFO typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE { - UCHAR ucTVStandard; //Same as TV standards defined above, + UCHAR ucTVStandard; //Same as TV standards defined above, UCHAR ucPadding[1]; }ATOM_ENCODER_ANALOG_ATTRIBUTE; typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE { UCHAR ucAttribute; //Same as other digital encoder attributes defined above - UCHAR ucPadding[1]; + UCHAR ucPadding[1]; }ATOM_ENCODER_DIGITAL_ATTRIBUTE; typedef union _ATOM_ENCODER_ATTRIBUTE @@ -7568,15 +7568,15 @@ typedef union _ATOM_ENCODER_ATTRIBUTE typedef struct _DVO_ENCODER_CONTROL_PARAMETERS { - USHORT usPixelClock; - USHORT usEncoderID; - UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. + USHORT usPixelClock; + USHORT usEncoderID; + UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT - ATOM_ENCODER_ATTRIBUTE usDevAttr; + ATOM_ENCODER_ATTRIBUTE usDevAttr; }DVO_ENCODER_CONTROL_PARAMETERS; typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION -{ +{ DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion }DVO_ENCODER_CONTROL_PS_ALLOCATION; @@ -7589,25 +7589,25 @@ typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 - + typedef struct _ATOM_XTMDS_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; - USHORT usSingleLinkMaxFrequency; + ATOM_COMMON_TABLE_HEADER sHeader; + USHORT usSingleLinkMaxFrequency; ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip - UCHAR ucXtransimitterID; + UCHAR ucXtransimitterID; UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported - UCHAR ucSequenceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters - // due to design. This ID is used to alert driver that the sequence is not "standard"! + UCHAR ucSequenceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters + // due to design. This ID is used to alert driver that the sequence is not "standard"! UCHAR ucMasterAddress; // Address to control Master xTMDS Chip UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip }ATOM_XTMDS_INFO; typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS -{ +{ UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... - UCHAR ucPadding[2]; + UCHAR ucPadding[2]; }DFP_DPMS_STATUS_CHANGE_PARAMETERS; /****************************Legacy Power Play Table Definitions **********************/ @@ -7624,8 +7624,8 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L -#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program - +#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program + #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L @@ -7635,22 +7635,22 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L -#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L +#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved -#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 +#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L -#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic +#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode -#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) +#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L @@ -7660,11 +7660,11 @@ typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L -#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. +#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L -#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L +#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L //ucTableFormatRevision=1 //ucTableContentRevision=1 @@ -7687,8 +7687,8 @@ typedef struct _ATOM_POWERMODE_INFO typedef struct _ATOM_POWERMODE_INFO_V2 { ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulMiscInfo2; - ULONG ulEngineClock; + ULONG ulMiscInfo2; + ULONG ulEngineClock; ULONG ulMemoryClock; UCHAR ucVoltageDropIndex; // index to GPIO table UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate @@ -7702,8 +7702,8 @@ typedef struct _ATOM_POWERMODE_INFO_V2 typedef struct _ATOM_POWERMODE_INFO_V3 { ULONG ulMiscInfo; //The power level should be arranged in ascending order - ULONG ulMiscInfo2; - ULONG ulEngineClock; + ULONG ulMiscInfo2; + ULONG ulEngineClock; ULONG ulMemoryClock; UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate @@ -7730,7 +7730,7 @@ typedef struct _ATOM_POWERMODE_INFO_V3 typedef struct _ATOM_POWERPLAY_INFO { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucOverdriveThermalController; UCHAR ucOverdriveI2cLine; UCHAR ucOverdriveIntBitmap; @@ -7742,7 +7742,7 @@ typedef struct _ATOM_POWERPLAY_INFO typedef struct _ATOM_POWERPLAY_INFO_V2 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucOverdriveThermalController; UCHAR ucOverdriveI2cLine; UCHAR ucOverdriveIntBitmap; @@ -7751,10 +7751,10 @@ typedef struct _ATOM_POWERPLAY_INFO_V2 UCHAR ucNumOfPowerModeEntries; ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; }ATOM_POWERPLAY_INFO_V2; - + typedef struct _ATOM_POWERPLAY_INFO_V3 { - ATOM_COMMON_TABLE_HEADER sHeader; + ATOM_COMMON_TABLE_HEADER sHeader; UCHAR ucOverdriveThermalController; UCHAR ucOverdriveI2cLine; UCHAR ucOverdriveIntBitmap; @@ -7765,14 +7765,14 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 }ATOM_POWERPLAY_INFO_V3; -// Following definitions are for compatibility issue in different SW components. +// Following definitions are for compatibility issue in different SW components. #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 -#define Object_Info Object_Header +#define Object_Info Object_Header #define AdjustARB_SEQ MC_InitParameter #define VRAM_GPIO_DetectionInfo VoltageObjectInfo -#define ASIC_VDDCI_Info ASIC_ProfilingInfo +#define ASIC_VDDCI_Info ASIC_ProfilingInfo #define ASIC_MVDDQ_Info MemoryTrainingInfo -#define SS_Info PPLL_SS_Info +#define SS_Info PPLL_SS_Info #define ASIC_MVDDC_Info ASIC_InternalSS_Info #define DispDevicePriorityInfo SaveRestoreInfo #define DispOutInfo TV_VideoMode @@ -7796,7 +7796,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX - + #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) @@ -7814,7 +7814,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 -#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE +#define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE #define ATOM_S3_DFP2I_ACTIVE 0x00000200L @@ -7833,14 +7833,14 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L -#define TMDS1XEncoderControl DVOEncoderControl +#define TMDS1XEncoderControl DVOEncoderControl #define DFP1XOutputControl DVOOutputControl #define ExternalDFPOutputControl DFP1XOutputControl #define EnableExternalTMDS_Encoder TMDS1XEncoderControl #define DFP1IOutputControl TMDSAOutputControl -#define DFP2IOutputControl LVTMAOutputControl +#define DFP2IOutputControl LVTMAOutputControl #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION @@ -7849,7 +7849,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION #define ucDac1Standard ucDacStandard -#define ucDac2Standard ucDacStandard +#define ucDac2Standard ucDacStandard #define TMDS1EncoderControl TMDSAEncoderControl #define TMDS2EncoderControl LVTMAEncoderControl @@ -7861,7 +7861,7 @@ typedef struct _ATOM_POWERPLAY_INFO_V3 //These two lines will be removed for sure in a few days, will follow up with Michael V. #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL -#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL +#define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE

[3/3] gpu/drm/radeon: Remove trailing spaces from ATOMBIOS header file

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