From patchwork Wed May 13 05:34:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 11544635 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 65A5781 for ; Wed, 13 May 2020 05:33:47 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A34A2054F for ; Wed, 13 May 2020 05:33:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4A34A2054F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D47B6E130; Wed, 13 May 2020 05:33:35 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id C23DC6E130; Wed, 13 May 2020 05:33:33 +0000 (UTC) IronPort-SDR: Q4SJ5ke+us8UqfarJ7FZHAMemjM/tDs1qr/z1a/zfgpkayhc51mZTDxn7wM14aaYOtRY67rdTn OKU3r7PcYM2A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2020 22:33:32 -0700 IronPort-SDR: ESAf0rmnDzvQeQS2+/c5KtLF41Jliph1jmmPCSwSOX0kAWUPpJwOXx9VcqaCtIq42+TCEGVQqL BzavpGHemfGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,386,1583222400"; d="scan'208";a="251133032" Received: from labuser-z97x-ud5h.jf.intel.com ([10.165.21.211]) by orsmga007.jf.intel.com with ESMTP; 12 May 2020 22:33:32 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH v5 2/3] drm/i915/dp: Attach and set drm connector VRR property Date: Tue, 12 May 2020 22:34:30 -0700 Message-Id: <20200513053431.2138-2-manasi.d.navare@intel.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20200513053431.2138-1-manasi.d.navare@intel.com> References: <20200513053431.2138-1-manasi.d.navare@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Manasi Navare , Aditya Swarup Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Aditya Swarup This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrjälä Cc: Jani Nikula Signed-off-by: Aditya Swarup Signed-off-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_dp.c | 27 +++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 67723dede1d1..8957a9f50f0e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6153,6 +6153,9 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + /*Reset the immutable VRR Capable property */ + drm_connector_set_vrr_capable_property(connector, + false); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -6260,6 +6263,23 @@ intel_dp_force(struct drm_connector *connector) intel_display_power_put(dev_priv, aux_domain, wakeref); } +bool intel_dp_is_vrr_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* + * DP Sink is capable of Variable refresh video timings if + * Ignore MSA bit is set in DPCD. + * EDID monitor range also should be atleast 10 for reasonable + * Adaptive sync/ VRR end user experience. + */ + return INTEL_GEN(dev_priv) >= 12 && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} + static int intel_dp_get_modes(struct drm_connector *connector) { struct intel_connector *intel_connector = to_intel_connector(connector); @@ -6268,6 +6288,10 @@ static int intel_dp_get_modes(struct drm_connector *connector) edid = intel_connector->detect_edid; if (edid) { int ret = intel_connector_update_modes(connector, edid); + + if (intel_dp_is_vrr_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); if (ret) return ret; } @@ -7354,6 +7378,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; } + + if (INTEL_GEN(dev_priv) >= 12) + drm_connector_attach_vrr_capable_property(connector); } static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6659ce15a693..aa7c1f530d5e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -14,6 +14,7 @@ enum pipe; enum port; struct drm_connector_state; struct drm_encoder; +struct drm_connector; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct intel_connector; @@ -119,6 +120,7 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, const struct drm_connector_state *conn_state); bool intel_digital_port_connected(struct intel_encoder *encoder); void intel_dp_process_phy_request(struct intel_dp *intel_dp); +bool intel_dp_is_vrr_capable(struct drm_connector *connector); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) {