From patchwork Fri Jul 3 08:07:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11641109 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 19BBD13BD for ; Fri, 3 Jul 2020 08:07:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E93A120885 for ; Fri, 3 Jul 2020 08:07:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="OpRTtEu1" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E93A120885 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EF8D86EABB; Fri, 3 Jul 2020 08:07:48 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F6DB6EABC for ; Fri, 3 Jul 2020 08:07:48 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id f18so23622294wrs.0 for ; Fri, 03 Jul 2020 01:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=88/c6iF/w8lZM2RfAJ05kcqHcvxKx4s6s4YqSMTo/Gg=; b=OpRTtEu1YUzm61nAFBqgskIMd88Be+93ByOAREtkdLAMHD6fOu8lMX31SWtiGSRe8V YCe1S4jwEnknbedY/uUfmARlMu5dOraGOgrcOGp4OihK3tPVHCwm6FO9ISioJknoBKh1 ee4GCKWviPhipNPeYe8MmVcQ1wc4CyG04DrhJINcIF5FJLsFHk5bM+7aO/dSU4C97pMa Z4qycifk2YxHqx7/+6jx62qkHupheHdN+tojfPxAXaW9Y7QUy3cv7f7JlgrASOi763ZF 6dJt2AARPRt+ZwnN3/co7u8FwWd8GWMkfhPtSUn7L9JE1+u/wYwJNkGvtf6ZqhVWFU74 95Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=88/c6iF/w8lZM2RfAJ05kcqHcvxKx4s6s4YqSMTo/Gg=; b=GlDIzu2kNroWM4QQ15vq7tdeKs6jjXUp1Kz3ZTFUZfyHdYAOlK5aHbBs6pRe5J7rLn PFHmkEt1uu94L1PvfgIQBVOwHYhu3u8tTP6Of6+WgXeXSpD0KSswuM6fFbTPUm9td/3c BZZN8/uj5iVXoASYdgTn6SERWHG1VO3RddKwK55XMZk7lrm2fmiZkdaYyFd5TzQX/fJB 6lfYrWbDntSjANBXNrkQcjTKccYqjrJ/pMLq5YBw3ZAFUYbisnRCqFBNWexMcZwm3DaI Bpq15/lbjr2g8sPZ7VzViyU3dFfWVee/obYOWx4qOZxhje9eeziJF9sURBq2EH0QMKjN 1tBg== X-Gm-Message-State: AOAM533GSrtPVtqFezF7KvjQGVm+m/GBdzLiTnn5iX8t7Nq3tHMO1KJV IeO/o9s72KH23iQEXaEpHM0jww== X-Google-Smtp-Source: ABdhPJyn6oWERky5OkZ9rDbGJk+8jGBt0LqFsQnUrJr1CFXyuOm8E+4l+YrLNN0mNq596ekxCXAffw== X-Received: by 2002:adf:c185:: with SMTP id x5mr38742923wre.403.1593763666711; Fri, 03 Jul 2020 01:07:46 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:6959:e617:6562:cabf]) by smtp.gmail.com with ESMTPSA id 1sm12682403wmf.0.2020.07.03.01.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2020 01:07:46 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch, dri-devel@lists.freedesktop.org Subject: [PATCH v9 6/6] drm/meson: crtc: handle commit of Amlogic FBC frames Date: Fri, 3 Jul 2020 10:07:28 +0200 Message-Id: <20200703080728.25207-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200703080728.25207-1-narmstrong@baylibre.com> References: <20200703080728.25207-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jianxin.pan@amlogic.com, Neil Armstrong , Kevin Hilman , linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since the VD1 Amlogic FBC decoder is now configured by the overlay driver, commit the right registers to decode the Amlogic FBC frame. Tested-by: Kevin Hilman Signed-off-by: Neil Armstrong Reviewed-by: Kevin Hilman --- drivers/gpu/drm/meson/meson_crtc.c | 118 +++++++++++++++++++++-------- 1 file changed, 88 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c index e66b6271ff58..2854272dc2d9 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -291,6 +291,10 @@ static void meson_crtc_enable_vd1(struct meson_drm *priv) VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | VPP_COLOR_MNG_ENABLE, priv->io_base + _REG(VPP_MISC)); + + writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1, + priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0, + priv->io_base + _REG(VIU_MISC_CTRL0)); } static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv) @@ -300,6 +304,10 @@ static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv) VD_BLEND_POSTBLD_SRC_VD1 | VD_BLEND_POSTBLD_PREMULT_EN, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); + + writel_relaxed(priv->viu.vd1_afbc ? + (VD1_AXI_SEL_AFBC | AFBC_VD1_SEL) : 0, + priv->io_base + _REG(VD1_AFBCD0_MISC_CTRL)); } void meson_crtc_irq(struct meson_drm *priv) @@ -383,36 +391,86 @@ void meson_crtc_irq(struct meson_drm *priv) /* Update the VD1 registers */ if (priv->viu.vd1_enabled && priv->viu.vd1_commit) { - switch (priv->viu.vd1_planes) { - case 3: - meson_canvas_config(priv->canvas, - priv->canvas_id_vd1_2, - priv->viu.vd1_addr2, - priv->viu.vd1_stride2, - priv->viu.vd1_height2, - MESON_CANVAS_WRAP_NONE, - MESON_CANVAS_BLKMODE_LINEAR, - MESON_CANVAS_ENDIAN_SWAP64); - /* fallthrough */ - case 2: - meson_canvas_config(priv->canvas, - priv->canvas_id_vd1_1, - priv->viu.vd1_addr1, - priv->viu.vd1_stride1, - priv->viu.vd1_height1, - MESON_CANVAS_WRAP_NONE, - MESON_CANVAS_BLKMODE_LINEAR, - MESON_CANVAS_ENDIAN_SWAP64); - /* fallthrough */ - case 1: - meson_canvas_config(priv->canvas, - priv->canvas_id_vd1_0, - priv->viu.vd1_addr0, - priv->viu.vd1_stride0, - priv->viu.vd1_height0, - MESON_CANVAS_WRAP_NONE, - MESON_CANVAS_BLKMODE_LINEAR, - MESON_CANVAS_ENDIAN_SWAP64); + if (priv->viu.vd1_afbc) { + writel_relaxed(priv->viu.vd1_afbc_head_addr, + priv->io_base + + _REG(AFBC_HEAD_BADDR)); + writel_relaxed(priv->viu.vd1_afbc_body_addr, + priv->io_base + + _REG(AFBC_BODY_BADDR)); + writel_relaxed(priv->viu.vd1_afbc_en, + priv->io_base + + _REG(AFBC_ENABLE)); + writel_relaxed(priv->viu.vd1_afbc_mode, + priv->io_base + + _REG(AFBC_MODE)); + writel_relaxed(priv->viu.vd1_afbc_size_in, + priv->io_base + + _REG(AFBC_SIZE_IN)); + writel_relaxed(priv->viu.vd1_afbc_dec_def_color, + priv->io_base + + _REG(AFBC_DEC_DEF_COLOR)); + writel_relaxed(priv->viu.vd1_afbc_conv_ctrl, + priv->io_base + + _REG(AFBC_CONV_CTRL)); + writel_relaxed(priv->viu.vd1_afbc_size_out, + priv->io_base + + _REG(AFBC_SIZE_OUT)); + writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl, + priv->io_base + + _REG(AFBC_VD_CFMT_CTRL)); + writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w, + priv->io_base + + _REG(AFBC_VD_CFMT_W)); + writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope, + priv->io_base + + _REG(AFBC_MIF_HOR_SCOPE)); + writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope, + priv->io_base + + _REG(AFBC_MIF_VER_SCOPE)); + writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope, + priv->io_base+ + _REG(AFBC_PIXEL_HOR_SCOPE)); + writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope, + priv->io_base + + _REG(AFBC_PIXEL_VER_SCOPE)); + writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h, + priv->io_base + + _REG(AFBC_VD_CFMT_H)); + } else { + switch (priv->viu.vd1_planes) { + case 3: + meson_canvas_config(priv->canvas, + priv->canvas_id_vd1_2, + priv->viu.vd1_addr2, + priv->viu.vd1_stride2, + priv->viu.vd1_height2, + MESON_CANVAS_WRAP_NONE, + MESON_CANVAS_BLKMODE_LINEAR, + MESON_CANVAS_ENDIAN_SWAP64); + fallthrough; + case 2: + meson_canvas_config(priv->canvas, + priv->canvas_id_vd1_1, + priv->viu.vd1_addr1, + priv->viu.vd1_stride1, + priv->viu.vd1_height1, + MESON_CANVAS_WRAP_NONE, + MESON_CANVAS_BLKMODE_LINEAR, + MESON_CANVAS_ENDIAN_SWAP64); + fallthrough; + case 1: + meson_canvas_config(priv->canvas, + priv->canvas_id_vd1_0, + priv->viu.vd1_addr0, + priv->viu.vd1_stride0, + priv->viu.vd1_height0, + MESON_CANVAS_WRAP_NONE, + MESON_CANVAS_BLKMODE_LINEAR, + MESON_CANVAS_ENDIAN_SWAP64); + } + + writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE)); } writel_relaxed(priv->viu.vd1_if0_gen_reg,