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[213.245.241.245]) by smtp.gmail.com with ESMTPSA id s8sm5545256wru.38.2020.07.09.07.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jul 2020 07:03:41 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Rob Herring , Tomeu Vizoso , Steven Price , Alyssa Rosenzweig , Viresh Kumar , Nishanth Menon , Stephen Boyd , Maxime Ripard , Chen-Yu Tsai Subject: [PATCH v3 13/14] [DO NOT MERGE] arm64: dts: allwinner: h6: Add GPU OPP table Date: Thu, 9 Jul 2020 16:03:21 +0200 Message-Id: <20200709140322.131320-14-peron.clem@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200709140322.131320-1-peron.clem@gmail.com> References: <20200709140322.131320-1-peron.clem@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Fri, 10 Jul 2020 07:52:58 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add an Operating Performance Points table for the GPU to enable Dynamic Voltage & Frequency Scaling on the H6. The voltage range is set with minival voltage set to the target and the maximal voltage set to 1.2V. This allow DVFS framework to work properly on board with fixed regulator. Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 80 ++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 8f514a2169aa..a69f9e09a829 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -174,6 +174,7 @@ gpu: gpu@1800000 { clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; clock-names = "core", "bus"; resets = <&ccu RST_BUS_GPU>; + operating-points-v2 = <&gpu_opp_table>; #cooling-cells = <2>; status = "disabled"; }; @@ -1036,4 +1037,83 @@ map0 { }; }; }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp@216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <810000 810000 1200000>; + }; + + opp@264000000 { + opp-hz = /bits/ 64 <264000000>; + opp-microvolt = <810000 810000 1200000>; + }; + + opp@312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <810000 810000 1200000>; + }; + + opp@336000000 { + opp-hz = /bits/ 64 <336000000>; + opp-microvolt = <810000 810000 1200000>; + }; + + opp@360000000 { + opp-hz = /bits/ 64 <360000000>; + opp-microvolt = <820000 820000 1200000>; + }; + + opp@384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt = <830000 830000 1200000>; + }; + + opp@408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <840000 840000 1200000>; + }; + + opp@420000000 { + opp-hz = /bits/ 64 <420000000>; + opp-microvolt = <850000 850000 1200000>; + }; + + opp@432000000 { + opp-hz = /bits/ 64 <432000000>; + opp-microvolt = <860000 860000 1200000>; + }; + + opp@456000000 { + opp-hz = /bits/ 64 <456000000>; + opp-microvolt = <870000 870000 1200000>; + }; + + opp@504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <890000 890000 1200000>; + }; + + opp@540000000 { + opp-hz = /bits/ 64 <540000000>; + opp-microvolt = <910000 910000 1200000>; + }; + + opp@576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-microvolt = <930000 930000 1200000>; + }; + + opp@624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <950000 950000 1200000>; + }; + + opp@756000000 { + opp-hz = /bits/ 64 <756000000>; + opp-microvolt = <1040000 1040000 1200000>; + }; + }; };