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[62.178.82.229]) by smtp.gmail.com with ESMTPSA id m14sm14046745wrx.76.2020.08.14.02.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Aug 2020 02:05:35 -0700 (PDT) From: Christian Gmeiner To: linux-kernel@vger.kernel.org Subject: [PATCH 4/4] drm/etnaviv: add pipe_select(..) helper Date: Fri, 14 Aug 2020 11:05:04 +0200 Message-Id: <20200814090512.151416-5-christian.gmeiner@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200814090512.151416-1-christian.gmeiner@gmail.com> References: <20200814090512.151416-1-christian.gmeiner@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , etnaviv@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Russell King , cphealy@gmail.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Replace the open coded pixel pipe selection pattern with a function. Signed-off-by: Christian Gmeiner --- drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c index b37459f022d7..bafdfe49c1d8 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c @@ -46,6 +46,14 @@ static u32 perf_reg_read(struct etnaviv_gpu *gpu, return gpu_read(gpu, domain->profile_read); } +static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe) +{ + clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); + clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(pipe); + + gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); +} + static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu, const struct etnaviv_pm_domain *domain, const struct etnaviv_pm_signal *signal) @@ -55,16 +63,12 @@ static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu, unsigned i; for (i = 0; i < gpu->identity.pixel_pipes; i++) { - clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); - clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i); - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); + pipe_select(gpu, clock, i); value += perf_reg_read(gpu, domain, signal); } /* switch back to pixel pipe 0 to prevent GPU hang */ - clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); - clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0); - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); + pipe_select(gpu, clock, 0); return value; } @@ -78,16 +82,12 @@ static u32 pipe_reg_read(struct etnaviv_gpu *gpu, unsigned i; for (i = 0; i < gpu->identity.pixel_pipes; i++) { - clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); - clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i); - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); + pipe_select(gpu, clock, i); value += gpu_read(gpu, signal->data); } /* switch back to pixel pipe 0 to prevent GPU hang */ - clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); - clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0); - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); + pipe_select(gpu, clock, 0); return value; }