@@ -281,6 +281,9 @@ int mipi_dsi_host_register(struct mipi_dsi_host *host)
{
struct device_node *node;
+ if (!host->bus_types)
+ host->bus_types = MIPI_DCS_BUS_TYPE_DSI;
+
for_each_available_child_of_node(host->dev->of_node, node) {
/* skip nodes without reg property */
if (!of_find_property(node, "reg", NULL))
@@ -323,6 +326,12 @@ int mipi_dsi_attach(struct mipi_dsi_device *dsi)
{
const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+ if (!dsi->bus_type)
+ dsi->bus_type = MIPI_DCS_BUS_TYPE_DSI;
+
+ if (!(dsi->bus_type & dsi->host->bus_types))
+ return -EINVAL;
+
if (!ops || !ops->attach)
return -ENOSYS;
@@ -63,6 +63,27 @@ struct mipi_dsi_packet {
int mipi_dsi_create_packet(struct mipi_dsi_packet *packet,
const struct mipi_dsi_msg *msg);
+/**
+ * enum mipi_dcs_bus_type - MIPI DCS bus types
+ * @MIPI_DCS_BUS_TYPE_DSI: MIPI DSI
+ * @MIPI_DCS_BUS_TYPE_DBI_SPI_C1: DBI with SPI carrier, 9 bits per word, with
+ * the data/command information in the 9th (MSB) bit
+ * @MIPI_DCS_BUS_TYPE_DBI_SPI_C2: DBI with SPI carrier, 16 bits per word, with
+ * the data/command information in the 9th bit, and 7 MSB bits of padding
+ * @MIPI_DCS_BUS_TYPE_DBI_SPI_C3: DBI with SPI carrier, 8 bits per word, with
+ * the data/command information carried by a separate GPIO
+ * @MIPI_DCS_BUS_TYPE_DBI_M6800: Motorola 6800 type parallel bus
+ * @MIPI_DCS_BUS_TYPE_DBI_I8080: Intel 8080 type parallel bus
+ */
+enum mipi_dcs_bus_type {
+ MIPI_DCS_BUS_TYPE_DSI = BIT(0),
+ MIPI_DCS_BUS_TYPE_DBI_SPI_C1 = BIT(1),
+ MIPI_DCS_BUS_TYPE_DBI_SPI_C2 = BIT(2),
+ MIPI_DCS_BUS_TYPE_DBI_SPI_C3 = BIT(3),
+ MIPI_DCS_BUS_TYPE_DBI_M6800 = BIT(4),
+ MIPI_DCS_BUS_TYPE_DBI_I8080 = BIT(5),
+};
+
/**
* struct mipi_dsi_host_ops - DSI bus operations
* @attach: attach DSI device to DSI host
@@ -94,11 +115,13 @@ struct mipi_dsi_host_ops {
* struct mipi_dsi_host - DSI host device
* @dev: driver model device node for this DSI host
* @ops: DSI host operations
+ * @bus_types: Bitmask of supported MIPI bus types (enum mipi_dcs_bus_type)
* @list: list management
*/
struct mipi_dsi_host {
struct device *dev;
const struct mipi_dsi_host_ops *ops;
+ unsigned int bus_types;
struct list_head list;
};
@@ -162,6 +185,7 @@ struct mipi_dsi_device_info {
* @host: DSI host for this peripheral
* @dev: driver model device node for this peripheral
* @name: DSI peripheral chip type
+ * @bus_type: MIPI bus type
* @channel: virtual channel assigned to the peripheral
* @format: pixel format for video mode
* @lanes: number of active data lanes
@@ -178,6 +202,7 @@ struct mipi_dsi_device {
struct device dev;
char name[DSI_DEV_NAME_SIZE];
+ enum mipi_dcs_bus_type bus_type;
unsigned int channel;
unsigned int lanes;
enum mipi_dsi_pixel_format format;
The current MIPI DSI framework can very well be used to support MIPI DBI panels. In order to add support for the various bus types supported by DBI, the DRM panel drivers should specify the bus type they will use, and the DSI host drivers should specify the bus types they are compatible with. The DSI host driver can then use the information provided by the DBI/DSI device driver, such as the bus type and the number of lanes, to configure its hardware properly. v2: - Remove the WARN_ON_ONCE() if (dbi->bus_types == 0), because it will trigger for every panel out there. Just default to MIPI_DCS_BUS_TYPE_DSI if the bitmask is not populated. - Create a 'enum mipi_dcs_bus_type' instead of macros - Rename values to avoid confusion about SPI modes Signed-off-by: Paul Cercueil <paul@crapouillou.net> --- drivers/gpu/drm/drm_mipi_dsi.c | 9 +++++++++ include/drm/drm_mipi_dsi.h | 25 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+)