| Message ID | 20201104103657.18007-6-s.nawrocki@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | None | expand |
Hi Sylwester, On Wed, Nov 4, 2020 at 7:37 PM Sylwester Nawrocki <s.nawrocki@samsung.com> wrote: > > This patch adds the following properties for Exynos4412 interconnect > bus nodes: > - interconnects: to declare connections between nodes in order to > guarantee PM QoS requirements between nodes, > - #interconnect-cells: required by the interconnect framework, > - samsung,data-clk-ratio: which allows to specify minimum data clock > frequency corresponding to requested bandwidth for each bus. > > Note that #interconnect-cells is always zero and node IDs are not > hardcoded anywhere. > > Signed-off-by: Artur Świgoń <a.swigon@samsung.com> > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > --- > Changes for v8: > - none. > > Changes for v7: > - adjusted to the DT property changes: "interconnects" instead > of "samsung,interconnect-parent", "samsung,data-clk-ratio" > instead of "bus-width". > > Changes for v6: > - added bus-width property in bus_dmc node. > > Changes for v5: > - adjust to renamed exynos,interconnect-parent-node property, > - add properties in common exynos4412.dtsi file rather than > in Odroid specific odroid4412-odroid-common.dtsi. > --- > arch/arm/boot/dts/exynos4412.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi > index e76881d..4999e68 100644 > --- a/arch/arm/boot/dts/exynos4412.dtsi > +++ b/arch/arm/boot/dts/exynos4412.dtsi > @@ -383,6 +383,8 @@ > clocks = <&clock CLK_DIV_DMC>; > clock-names = "bus"; > operating-points-v2 = <&bus_dmc_opp_table>; > + samsung,data-clock-ratio = <4>; > + #interconnect-cells = <0>; > status = "disabled"; > }; > > @@ -452,6 +454,8 @@ > clocks = <&clock CLK_DIV_GDL>; > clock-names = "bus"; > operating-points-v2 = <&bus_leftbus_opp_table>; > + interconnects = <&bus_dmc>; > + #interconnect-cells = <0>; > status = "disabled"; > }; > > @@ -468,6 +472,8 @@ > clocks = <&clock CLK_ACLK160>; > clock-names = "bus"; > operating-points-v2 = <&bus_display_opp_table>; > + interconnects = <&bus_leftbus &bus_dmc>; > + #interconnect-cells = <0>; > status = "disabled"; > }; > > -- > 2.7.4 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
On Wed, Nov 04, 2020 at 11:36:55AM +0100, Sylwester Nawrocki wrote: > This patch adds the following properties for Exynos4412 interconnect > bus nodes: > - interconnects: to declare connections between nodes in order to > guarantee PM QoS requirements between nodes, > - #interconnect-cells: required by the interconnect framework, > - samsung,data-clk-ratio: which allows to specify minimum data clock > frequency corresponding to requested bandwidth for each bus. > > Note that #interconnect-cells is always zero and node IDs are not > hardcoded anywhere. > > Signed-off-by: Artur Świgoń <a.swigon@samsung.com> > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> > --- > Changes for v8: > - none. > > Changes for v7: > - adjusted to the DT property changes: "interconnects" instead > of "samsung,interconnect-parent", "samsung,data-clk-ratio" > instead of "bus-width". > > Changes for v6: > - added bus-width property in bus_dmc node. > > Changes for v5: > - adjust to renamed exynos,interconnect-parent-node property, > - add properties in common exynos4412.dtsi file rather than > in Odroid specific odroid4412-odroid-common.dtsi. > --- > arch/arm/boot/dts/exynos4412.dtsi | 6 ++++++ Thanks, applied with Chanwoo's tags. Best regards, Krzysztof
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index e76881d..4999e68 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -383,6 +383,8 @@ clocks = <&clock CLK_DIV_DMC>; clock-names = "bus"; operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; status = "disabled"; }; @@ -452,6 +454,8 @@ clocks = <&clock CLK_DIV_GDL>; clock-names = "bus"; operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; status = "disabled"; }; @@ -468,6 +472,8 @@ clocks = <&clock CLK_ACLK160>; clock-names = "bus"; operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; status = "disabled"; };