| Message ID | 20210106192800.164052-2-giulio.benetti@micronovasrl.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/sun4i: fix DCLK and improve its handling | expand |
Dne sreda, 06. januar 2021 ob 20:27:59 CET je Giulio Benetti napisal(a): > During commit "88bc4178568b8e0331143cc0616640ab72f0cba1" DRM_BUS_FLAG_* Please use same commit referencing approach as for "Fixes" tag. > macros have been changed to avoid ambiguity but just because of this > ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning > _SAMPLE_ not _DRIVE_. This lead to DLCK inversion, so let's swap DCLK > phase to fix it. > Add Fixes tag here. Best regards, Jernej > Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> > --- > drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/ sun4i_tcon.c > index eaaf5d70e352..52598bb0fb0b 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > @@ -585,10 +585,10 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, > * and DOTCLOCK drivers. > */ > if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) > - clk_set_phase(tcon->dclk, 240); > + clk_set_phase(tcon->dclk, 0); > > if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) > - clk_set_phase(tcon->dclk, 0); > + clk_set_phase(tcon->dclk, 240); > > regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, > SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | > -- > 2.25.1 > >
From: Giulio Benetti <giulio.benetti@micronovasrl.com>
First patch is a tested by me fix, while the second need testing to
understand if it works correctly with any sunxi SoC with DE peripheral.
Already tested SoCs are:
- A20
- A33
Need testing:
- A10
- A10s
- A13
Giulio Benetti (2):
drm/sun4i: tcon: fix inverted DCLK polarity
drm/sun4i: tcon: improve DCLK polarity handling
drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +-------------------
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
2 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index eaaf5d70e352..52598bb0fb0b 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -585,10 +585,10 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, * and DOTCLOCK drivers. */ if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) - clk_set_phase(tcon->dclk, 240); + clk_set_phase(tcon->dclk, 0); if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) - clk_set_phase(tcon->dclk, 0); + clk_set_phase(tcon->dclk, 240); regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
During commit "88bc4178568b8e0331143cc0616640ab72f0cba1" DRM_BUS_FLAG_* macros have been changed to avoid ambiguity but just because of this ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning _SAMPLE_ not _DRIVE_. This lead to DLCK inversion, so let's swap DCLK phase to fix it. Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)