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Tue, 26 Jan 2021 20:54:53 -0800 (PST) Received: from hsinyi-z840.tpe.corp.google.com ([2401:fa00:1:10:e0a5:d2fc:aaad:1e4a]) by smtp.gmail.com with ESMTPSA id a141sm684484pfa.189.2021.01.26.20.54.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Jan 2021 20:54:52 -0800 (PST) From: Hsin-Yi Wang To: CK Hu , Philipp Zabel , Matthias Brugger Subject: [PATCH v10 7/9] drm/mediatek: enable dither function Date: Wed, 27 Jan 2021 12:54:20 +0800 Message-Id: <20210127045422.2418917-8-hsinyi@chromium.org> X-Mailer: git-send-email 2.30.0.280.ga3ce27912f-goog In-Reply-To: <20210127045422.2418917-1-hsinyi@chromium.org> References: <20210127045422.2418917-1-hsinyi@chromium.org> MIME-Version: 1.0 X-Mailman-Approved-At: Wed, 27 Jan 2021 08:29:46 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Yongqiang Niu , David Airlie , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Yongqiang Niu for 5 or 6 bpc panel, we need enable dither function to improve the display quality Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 37 ++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 8173f709272be..ee54505412dcd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -53,7 +53,9 @@ #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) +#define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 +#define DITHER_REG(idx) (0x100 + (idx) * 4) #define LUT_10BIT_MASK 0x03ff @@ -313,8 +315,41 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + bool enable = true; + + const u32 dither_setting[] = { + 0x00000000, /* 5 */ + 0x00003002, /* 6 */ + 0x00000000, /* 7 */ + 0x00000000, /* 8 */ + 0x00000000, /* 9 */ + 0x00000000, /* 10 */ + 0x00000000, /* 11 */ + 0x00000011, /* 12 */ + 0x00000000, /* 13 */ + 0x00000000, /* 14 */ + }; + + if (bpc == 6) { + mtk_ddp_write(cmdq_pkt, 0x40400001, &priv->cmdq_reg, priv->regs, DITHER_REG(15)); + mtk_ddp_write(cmdq_pkt, 0x40404040, &priv->cmdq_reg, priv->regs, DITHER_REG(16)); + } else if (bpc == 5) { + mtk_ddp_write(cmdq_pkt, 0x50500001, &priv->cmdq_reg, priv->regs, DITHER_REG(15)); + mtk_ddp_write(cmdq_pkt, 0x50504040, &priv->cmdq_reg, priv->regs, DITHER_REG(16)); + } else { + enable = false; + } + + if (enable) { + u32 idx; + + for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++) + mtk_ddp_write(cmdq_pkt, dither_setting[idx], &priv->cmdq_reg, priv->regs, + DITHER_REG(idx + 5)); + } + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); + mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); } static void mtk_dither_start(struct device *dev)