| Message ID | 20210204064842.11595-3-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | HDMI2.1 PCON Misc Fixes | expand |
On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote: > Currently the FRL training mode (Concurrent, Sequential) and > training type (Normal, Extended) are not defined properly and > are passed as bool values in drm_helpers for pcon > configuration for FRL training. > > This patch: > -Defines FRL training type and link bring up sequence mode as enum. > -Fixes the drm_helpers for FRL Training configuration to use these enums. > -Modifies the calls to the above drm_helpers in i915/intel_dp as per the > above change. > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > drivers/gpu/drm/drm_dp_helper.c | 18 +++++----- > drivers/gpu/drm/i915/display/intel_dp.c | 10 +++--- > include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++-- > 3 files changed, 56 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c > index eedbb48815b7..2ca4ab5af470 100644 > --- a/drivers/gpu/drm/drm_dp_helper.c > +++ b/drivers/gpu/drm/drm_dp_helper.c > @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); > * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 > * @aux: DisplayPort AUX channel > * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink > - * @concurrent_mode: true if concurrent mode or operation is required, > - * false otherwise. > + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. > * > * Returns 0 if success, else returns negative error code. > */ > > int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > - bool concurrent_mode) > + enum dp_pcon_frl_train_mode frl_mode) > { > int ret; > u8 buf; > @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > if (ret < 0) > return ret; > > - if (concurrent_mode) > + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT) > buf |= DP_PCON_ENABLE_CONCURRENT_LINK; > else > buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; > @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); > * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 > * @aux: DisplayPort AUX channel > * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink > - * @extended_train_mode : true for Extended Mode, false for Normal Mode. > - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting > - * from min, and stops when link training is successful. In Extended mode, all > - * frl bw selected in the mask are trained by the PCON. > + * @frl_type : FRL training type, can be Extended, or Normal. > * > * Returns 0 if success, else returns negative error code. > */ > int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, > - bool extended_train_mode) > + enum dp_pcon_frl_train_type frl_type) > { > int ret; > u8 buf = max_frl_mask; > > - if (extended_train_mode) > + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED) > buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; > + else > + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; These names are annoyingly close to each other. Prettu much guaranteed to mix them up at some point. We should try to come up something a bit more distinctive for the enum, or just forget the enum and use the register values directly. > > ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); > if (ret < 0) > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 2b83f0f433a2..1962d6dd8641 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) > > static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) > { > -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) > -#define PCON_CONCURRENT_MODE (1 > 0) > -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE > -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE > #define TIMEOUT_FRL_READY_MS 500 > #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 > > @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) > return -ETIMEDOUT; > > max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); > - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); > + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, > + DP_PCON_FRL_MODE_SEQUENTIAL); > if (ret < 0) > return ret; > - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); > + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, > + DP_PCON_FRL_TRAIN_NORMAL); > if (ret < 0) > return ret; > ret = drm_dp_pcon_frl_enable(&intel_dp->aux); > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index edffd1dcca3e..c3f56e87a5ec 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -1646,6 +1646,48 @@ enum dp_content_type { > DP_CONTENT_TYPE_GAME = 0x04, > }; > > +/** > + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type > + * > + * This enum is used to select FRL training type for FRL training between > + * an HDMI2.1 PCON and an HDMI2.1 sink. > + * > + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification > + * Sec 6.1 Table-3. > + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK > + * starting from min, and stops when link training is successful. > + * In Extended FRL training, all frl bw selected in the mask are trained by the > + * PCON. > + * > + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal > + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended > + */ > +enum dp_pcon_frl_train_type { > + DP_PCON_FRL_TRAIN_NORMAL = 0, > + DP_PCON_FRL_TRAIN_EXTENDED = 1, > +}; > + > +/** > + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode > + * > + * This enum is used to select mode for FRL Link bringup between an HDMI2.1 > + * PCON and an HDMI2.1 sink. > + * > + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification > + * Sec 6.1 Table-3. > + * In Concurrent Mode, the FRL link bring up can be done along with DP Link > + * training. In Sequential mode, the FRL link bring up is done prior to the > + * DP Link training. > + * > + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode > + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode > + */ > + > +enum dp_pcon_frl_train_mode { > + DP_PCON_FRL_MODE_SEQUENTIAL = 0, > + DP_PCON_FRL_MODE_CONCURRENT = 1, > +}; > + > /** > * struct drm_dp_vsc_sdp - drm DP VSC SDP > * > @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], > int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); > bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); > int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, > - bool concurrent_mode); > + enum dp_pcon_frl_train_mode frl_mode); > int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, > - bool extended_train_mode); > + enum dp_pcon_frl_train_type frl_type); > int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); > int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); > > -- > 2.29.2
On 2/6/2021 1:30 AM, Ville Syrjälä wrote: > On Thu, Feb 04, 2021 at 12:18:41PM +0530, Ankit Nautiyal wrote: >> Currently the FRL training mode (Concurrent, Sequential) and >> training type (Normal, Extended) are not defined properly and >> are passed as bool values in drm_helpers for pcon >> configuration for FRL training. >> >> This patch: >> -Defines FRL training type and link bring up sequence mode as enum. >> -Fixes the drm_helpers for FRL Training configuration to use these enums. >> -Modifies the calls to the above drm_helpers in i915/intel_dp as per the >> above change. >> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> >> --- >> drivers/gpu/drm/drm_dp_helper.c | 18 +++++----- >> drivers/gpu/drm/i915/display/intel_dp.c | 10 +++--- >> include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++-- >> 3 files changed, 56 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c >> index eedbb48815b7..2ca4ab5af470 100644 >> --- a/drivers/gpu/drm/drm_dp_helper.c >> +++ b/drivers/gpu/drm/drm_dp_helper.c >> @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); >> * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 >> * @aux: DisplayPort AUX channel >> * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink >> - * @concurrent_mode: true if concurrent mode or operation is required, >> - * false otherwise. >> + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. >> * >> * Returns 0 if success, else returns negative error code. >> */ >> >> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, >> - bool concurrent_mode) >> + enum dp_pcon_frl_train_mode frl_mode) >> { >> int ret; >> u8 buf; >> @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, >> if (ret < 0) >> return ret; >> >> - if (concurrent_mode) >> + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT) >> buf |= DP_PCON_ENABLE_CONCURRENT_LINK; >> else >> buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; >> @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); >> * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 >> * @aux: DisplayPort AUX channel >> * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink >> - * @extended_train_mode : true for Extended Mode, false for Normal Mode. >> - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting >> - * from min, and stops when link training is successful. In Extended mode, all >> - * frl bw selected in the mask are trained by the PCON. >> + * @frl_type : FRL training type, can be Extended, or Normal. >> * >> * Returns 0 if success, else returns negative error code. >> */ >> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, >> - bool extended_train_mode) >> + enum dp_pcon_frl_train_type frl_type) >> { >> int ret; >> u8 buf = max_frl_mask; >> >> - if (extended_train_mode) >> + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED) >> buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; >> + else >> + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; > These names are annoyingly close to each other. Prettu much > guaranteed to mix them up at some point. We should try to come > up something a bit more distinctive for the enum, or just forget > the enum and use the register values directly. Agreed. Sent next version of the patch, dropping the enum and used only appropriate register values. Thanks & Regards, Ankit >> >> ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); >> if (ret < 0) >> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c >> index 2b83f0f433a2..1962d6dd8641 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dp.c >> +++ b/drivers/gpu/drm/i915/display/intel_dp.c >> @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) >> >> static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) >> { >> -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) >> -#define PCON_CONCURRENT_MODE (1 > 0) >> -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE >> -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE >> #define TIMEOUT_FRL_READY_MS 500 >> #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 >> >> @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) >> return -ETIMEDOUT; >> >> max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); >> - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); >> + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, >> + DP_PCON_FRL_MODE_SEQUENTIAL); >> if (ret < 0) >> return ret; >> - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); >> + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, >> + DP_PCON_FRL_TRAIN_NORMAL); >> if (ret < 0) >> return ret; >> ret = drm_dp_pcon_frl_enable(&intel_dp->aux); >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> index edffd1dcca3e..c3f56e87a5ec 100644 >> --- a/include/drm/drm_dp_helper.h >> +++ b/include/drm/drm_dp_helper.h >> @@ -1646,6 +1646,48 @@ enum dp_content_type { >> DP_CONTENT_TYPE_GAME = 0x04, >> }; >> >> +/** >> + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type >> + * >> + * This enum is used to select FRL training type for FRL training between >> + * an HDMI2.1 PCON and an HDMI2.1 sink. >> + * >> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification >> + * Sec 6.1 Table-3. >> + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK >> + * starting from min, and stops when link training is successful. >> + * In Extended FRL training, all frl bw selected in the mask are trained by the >> + * PCON. >> + * >> + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal >> + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended >> + */ >> +enum dp_pcon_frl_train_type { >> + DP_PCON_FRL_TRAIN_NORMAL = 0, >> + DP_PCON_FRL_TRAIN_EXTENDED = 1, >> +}; >> + >> +/** >> + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode >> + * >> + * This enum is used to select mode for FRL Link bringup between an HDMI2.1 >> + * PCON and an HDMI2.1 sink. >> + * >> + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification >> + * Sec 6.1 Table-3. >> + * In Concurrent Mode, the FRL link bring up can be done along with DP Link >> + * training. In Sequential mode, the FRL link bring up is done prior to the >> + * DP Link training. >> + * >> + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode >> + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode >> + */ >> + >> +enum dp_pcon_frl_train_mode { >> + DP_PCON_FRL_MODE_SEQUENTIAL = 0, >> + DP_PCON_FRL_MODE_CONCURRENT = 1, >> +}; >> + >> /** >> * struct drm_dp_vsc_sdp - drm DP VSC SDP >> * >> @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], >> int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); >> bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); >> int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, >> - bool concurrent_mode); >> + enum dp_pcon_frl_train_mode frl_mode); >> int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, >> - bool extended_train_mode); >> + enum dp_pcon_frl_train_type frl_type); >> int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); >> int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); >> >> -- >> 2.29.2
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index eedbb48815b7..2ca4ab5af470 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -2635,14 +2635,13 @@ EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 * @aux: DisplayPort AUX channel * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink - * @concurrent_mode: true if concurrent mode or operation is required, - * false otherwise. + * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode) + enum dp_pcon_frl_train_mode frl_mode) { int ret; u8 buf; @@ -2651,7 +2650,7 @@ int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, if (ret < 0) return ret; - if (concurrent_mode) + if (frl_mode == DP_PCON_FRL_MODE_CONCURRENT) buf |= DP_PCON_ENABLE_CONCURRENT_LINK; else buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; @@ -2694,21 +2693,20 @@ EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 * @aux: DisplayPort AUX channel * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink - * @extended_train_mode : true for Extended Mode, false for Normal Mode. - * In Normal mode, the PCON tries each frl bw from the max_frl_mask starting - * from min, and stops when link training is successful. In Extended mode, all - * frl bw selected in the mask are trained by the PCON. + * @frl_type : FRL training type, can be Extended, or Normal. * * Returns 0 if success, else returns negative error code. */ int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode) + enum dp_pcon_frl_train_type frl_type) { int ret; u8 buf = max_frl_mask; - if (extended_train_mode) + if (frl_type == DP_PCON_FRL_TRAIN_EXTENDED) buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; + else + buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); if (ret < 0) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2b83f0f433a2..1962d6dd8641 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2560,10 +2560,6 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) { -#define PCON_EXTENDED_TRAIN_MODE (1 > 0) -#define PCON_CONCURRENT_MODE (1 > 0) -#define PCON_SEQUENTIAL_MODE !PCON_CONCURRENT_MODE -#define PCON_NORMAL_TRAIN_MODE !PCON_EXTENDED_TRAIN_MODE #define TIMEOUT_FRL_READY_MS 500 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 @@ -2597,10 +2593,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) return -ETIMEDOUT; max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); - ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, PCON_SEQUENTIAL_MODE); + ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, + DP_PCON_FRL_MODE_SEQUENTIAL); if (ret < 0) return ret; - ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, PCON_NORMAL_TRAIN_MODE); + ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, + DP_PCON_FRL_TRAIN_NORMAL); if (ret < 0) return ret; ret = drm_dp_pcon_frl_enable(&intel_dp->aux); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index edffd1dcca3e..c3f56e87a5ec 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1646,6 +1646,48 @@ enum dp_content_type { DP_CONTENT_TYPE_GAME = 0x04, }; +/** + * enum dp_pcon_frl_train_type - drm DP PCON FRL Training Type + * + * This enum is used to select FRL training type for FRL training between + * an HDMI2.1 PCON and an HDMI2.1 sink. + * + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification + * Sec 6.1 Table-3. + * In Normal FRL training, the PCON tries each frl bw from the MAX FRL MASK + * starting from min, and stops when link training is successful. + * In Extended FRL training, all frl bw selected in the mask are trained by the + * PCON. + * + * @DP_PCON_FRL_TRAIN_NORMAL: FRL training type Normal + * @DP_PCON_FRL_TRAIN_EXTENDED: FRL training type Extended + */ +enum dp_pcon_frl_train_type { + DP_PCON_FRL_TRAIN_NORMAL = 0, + DP_PCON_FRL_TRAIN_EXTENDED = 1, +}; + +/** + * enum dp_pcon_frl_train_mode - drm DP PCON FRL Training Mode + * + * This enum is used to select mode for FRL Link bringup between an HDMI2.1 + * PCON and an HDMI2.1 sink. + * + * It is based on VESA DP-to-HDMI Protocol Converter (PCON) Specification + * Sec 6.1 Table-3. + * In Concurrent Mode, the FRL link bring up can be done along with DP Link + * training. In Sequential mode, the FRL link bring up is done prior to the + * DP Link training. + * + * @DP_PCON_FRL_MODE_SEQUENTIAL: Sequential Training mode + * @DP_PCON_FRL_MODE_CONCURRENT: Concurrent Training mode + */ + +enum dp_pcon_frl_train_mode { + DP_PCON_FRL_MODE_SEQUENTIAL = 0, + DP_PCON_FRL_MODE_CONCURRENT = 1, +}; + /** * struct drm_dp_vsc_sdp - drm DP VSC SDP * @@ -2149,9 +2191,9 @@ int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - bool concurrent_mode); + enum dp_pcon_frl_train_mode frl_mode); int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - bool extended_train_mode); + enum dp_pcon_frl_train_type frl_type); int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
Currently the FRL training mode (Concurrent, Sequential) and training type (Normal, Extended) are not defined properly and are passed as bool values in drm_helpers for pcon configuration for FRL training. This patch: -Defines FRL training type and link bring up sequence mode as enum. -Fixes the drm_helpers for FRL Training configuration to use these enums. -Modifies the calls to the above drm_helpers in i915/intel_dp as per the above change. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> --- drivers/gpu/drm/drm_dp_helper.c | 18 +++++----- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++--- include/drm/drm_dp_helper.h | 46 +++++++++++++++++++++++-- 3 files changed, 56 insertions(+), 18 deletions(-)