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[82.24.248.100]) by smtp.gmail.com with ESMTPSA id o1sm2121808eds.26.2021.03.05.10.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Mar 2021 10:39:35 -0800 (PST) From: Emil Velikov To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/7] media: hantro: use G1_REG_INTERRUPT directly for the mpeg2 Date: Fri, 5 Mar 2021 18:39:18 +0000 Message-Id: <20210305183924.1754026-2-emil.l.velikov@gmail.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210305183924.1754026-1-emil.l.velikov@gmail.com> References: <20210305183924.1754026-1-emil.l.velikov@gmail.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nicolas Ferre , linux-rockchip@lists.infradead.org, kernel@collabora.com, Ezequiel Garcia , linux-media@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Emil Velikov Use the register directly over the existing SWREG(). Ideally we'll port the driver away from the local registers, but for now this is enough. For context - I was reading through the IRQ register handling across the variants. Cc: Ezequiel Garcia Cc: Philipp Zabel Cc: linux-media@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Emil Velikov --- drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c b/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c index 6386a3989bfe..0fd306806f16 100644 --- a/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c @@ -10,6 +10,7 @@ #include #include "hantro.h" #include "hantro_hw.h" +#include "hantro_g1_regs.h" #define G1_SWREG(nr) ((nr) * 4) @@ -20,7 +21,6 @@ #define G1_REG_REFER2_BASE G1_SWREG(16) #define G1_REG_REFER3_BASE G1_SWREG(17) #define G1_REG_QTABLE_BASE G1_SWREG(40) -#define G1_REG_DEC_E(v) ((v) ? BIT(0) : 0) #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) @@ -246,6 +246,5 @@ void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx) hantro_end_prepare_run(ctx); - reg = G1_REG_DEC_E(1); - vdpu_write(vpu, reg, G1_SWREG(1)); + vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); }