[16/21] drm/msm/dpu: call hw_intf ops directly

Message ID	20210324150024.2768215-17-dmitry.baryshkov@linaro.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=6sh/=IW=lists.freedesktop.org=dri-devel-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7940861A06 From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>, Jonathan Marek <jonathan@marek.ca> Subject: [PATCH 16/21] drm/msm/dpu: call hw_intf ops directly Date: Wed, 24 Mar 2021 18:00:19 +0300 Message-Id: <20210324150024.2768215-17-dmitry.baryshkov@linaro.org> In-Reply-To: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> References: <20210324150024.2768215-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: list Cc: Stephen Boyd <sboyd@kernel.org>, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie <airlied@linux.ie>, freedreno@lists.freedesktop.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" <dri-devel-bounces@lists.freedesktop.org>
Series	drm/msm/dpu: cleanup callbacks, resource manager \| expand [00/21] drm/msm/dpu: cleanup callbacks, resource manager [01/21] drm/msm/dpu: enable DPU_SSPP_QOS_8LVL for SM8250 [02/21] drm/msm/dpu: remove unused dpu_hw_blk features [03/21] drm/msm/dpu: drop dpu_hw_blk_destroy function [04/21] drm/msm/dpu: get DSPP blocks directly rather than through RM [05/21] drm/msm/dpu: get MERGE_3D blocks directly rather than through RM [06/21] drm/msm/dpu: get PINGPONG blocks directly rather than through RM [07/21] drm/msm/dpu: drop unused lm_max_width from RM [08/21] drm/msm/dpu: simplify peer LM handling [09/21] drm/msm/dpu: drop dpu_encoder_phys's get_hw_resources() callback [10/21] drm/msm/dpu: drop dpu_hw_lm_setup_blend_config() [11/21] drm/msm/dpu: call hw_lm ops directly [12/21] drm/msm/dpu: call hw_dspp ops directly [13/21] drm/msm/dpu: hw_pp: make setup_dither mandatory [14/21] drm/msm/dpu: call hw_pingpong ops directly [15/21] drm/msm/dpu: call hw_merge_3d ops directly [16/21] drm/msm/dpu: call hw_intf ops directly [17/21] drm/msm/dpu: call hw_top ops directly [18/21] drm/msm/dpu: hw_vbif: make set_qos_remap mandatory [19/21] drm/msm/dpu: call hw_vbif ops directly [20/21] drm/msm/dpu: fix smart dma support [21/21] drm/msm/dpu: call hw_intr ops directly

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 868bb2f06125..e7a30246eb00 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -202,9 +202,6 @@ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, u32 vfp_fetch_start_vsync_counter = 0; unsigned long lock_flags; - if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) - return; - vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing); if (vfp_fetch_lines) { vert_total = get_vertical_total(timing); @@ -220,7 +217,7 @@ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, vfp_fetch_lines, vfp_fetch_start_vsync_counter); spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f); + dpu_hw_intf_setup_prg_fetch(phys_enc->hw_intf, &f); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); } @@ -253,10 +250,6 @@ static void dpu_encoder_phys_vid_setup_timing_engine( } mode = phys_enc->cached_mode; - if (!phys_enc->hw_intf->ops.setup_timing_gen) { - DPU_ERROR("timing engine setup is not supported\n"); - return; - } DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); drm_mode_debug_printmodeline(&mode); @@ -287,13 +280,12 @@ static void dpu_encoder_phys_vid_setup_timing_engine( intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, + dpu_hw_intf_setup_timing_engine(phys_enc->hw_intf, &timing_params, fmt); phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); /* setup which pp blk will connect to this intf */ - if (phys_enc->hw_intf->ops.bind_pingpong_blk) - phys_enc->hw_intf->ops.bind_pingpong_blk( + dpu_hw_intf_bind_pingpong_blk( phys_enc->hw_intf, true, phys_enc->hw_pp->idx); @@ -440,9 +432,6 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) DPU_DEBUG_VIDENC(phys_enc, "\n"); - if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) - return; - dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx); dpu_encoder_phys_vid_setup_timing_engine(phys_enc); @@ -560,16 +549,13 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) return; } - if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) - return; - if (phys_enc->enable_state == DPU_ENC_DISABLED) { DPU_ERROR("already disabled\n"); return; } spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); + dpu_hw_intf_enable_timing_engine(phys_enc->hw_intf, 0); if (dpu_encoder_phys_vid_is_master(phys_enc)) dpu_encoder_phys_inc_pending(phys_enc); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); @@ -608,7 +594,7 @@ static void dpu_encoder_phys_vid_handle_post_kickoff( trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent), phys_enc->hw_intf->idx - INTF_0); spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1); + dpu_hw_intf_enable_timing_engine(phys_enc->hw_intf, 1); spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc->enable_state = DPU_ENC_ENABLED; } @@ -642,10 +628,10 @@ static int dpu_encoder_phys_vid_get_line_count( if (!dpu_encoder_phys_vid_is_master(phys_enc)) return -EINVAL; - if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) + if (!phys_enc->hw_intf) return -EINVAL; - return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); + return dpu_hw_intf_get_line_count(phys_enc->hw_intf); } static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 8df75936d906..3988700dcc85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -80,7 +80,7 @@ static const struct dpu_intf_cfg *_intf_offset(enum dpu_intf intf, return ERR_PTR(-EINVAL); } -static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, +void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, const struct intf_timing_params *p, const struct dpu_format *fmt) { @@ -197,7 +197,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); } -static void dpu_hw_intf_enable_timing_engine( +void dpu_hw_intf_enable_timing_engine( struct dpu_hw_intf *intf, u8 enable) { @@ -206,7 +206,7 @@ static void dpu_hw_intf_enable_timing_engine( DPU_REG_WRITE(c, INTF_TIMING_ENGINE_EN, enable != 0); } -static void dpu_hw_intf_setup_prg_fetch( +void dpu_hw_intf_setup_prg_fetch( struct dpu_hw_intf *intf, const struct intf_prog_fetch *fetch) { @@ -230,7 +230,7 @@ static void dpu_hw_intf_setup_prg_fetch( DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); } -static void dpu_hw_intf_bind_pingpong_blk( +void dpu_hw_intf_bind_pingpong_blk( struct dpu_hw_intf *intf, bool enable, const enum dpu_pingpong pp) @@ -238,6 +238,9 @@ static void dpu_hw_intf_bind_pingpong_blk( struct dpu_hw_blk_reg_map *c = &intf->hw; u32 mux_cfg; + if (!test_bit(DPU_INTF_INPUT_CTRL, &intf->cap->features)) + return; + mux_cfg = DPU_REG_READ(c, INTF_MUX); mux_cfg &= ~0xf; @@ -249,7 +252,7 @@ static void dpu_hw_intf_bind_pingpong_blk( DPU_REG_WRITE(c, INTF_MUX, mux_cfg); } -static void dpu_hw_intf_get_status( +void dpu_hw_intf_get_status( struct dpu_hw_intf *intf, struct intf_status *s) { @@ -265,7 +268,7 @@ static void dpu_hw_intf_get_status( } } -static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) +u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) { struct dpu_hw_blk_reg_map *c; @@ -277,18 +280,6 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf) return DPU_REG_READ(c, INTF_LINE_COUNT); } -static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, - unsigned long cap) -{ - ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; - ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; - ops->get_status = dpu_hw_intf_get_status; - ops->enable_timing = dpu_hw_intf_enable_timing_engine; - ops->get_line_count = dpu_hw_intf_get_line_count; - if (cap & BIT(DPU_INTF_INPUT_CTRL)) - ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; -} - struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, void __iomem *addr, const struct dpu_mdss_cfg *m) @@ -313,7 +304,6 @@ struct dpu_hw_intf *dpu_hw_intf_init(enum dpu_intf idx, c->idx = idx; c->cap = cfg; c->mdss = m; - _setup_intf_ops(&c->ops, c->cap->features); dpu_hw_blk_init(&c->base, DPU_HW_BLK_INTF, idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 0ead64d3f63d..8661571fec67 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -44,37 +44,35 @@ struct intf_status { u32 line_count; /* current line count including blanking */ }; -/** - * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions +/* * Assumption is these functions will be called after clocks are enabled - * @ setup_timing_gen : programs the timing engine - * @ setup_prog_fetch : enables/disables the programmable fetch logic - * @ enable_timing: enable/disable timing engine - * @ get_status: returns if timing engine is enabled or not - * @ get_line_count: reads current vertical line counter - * @bind_pingpong_blk: enable/disable the connection with pingpong which will - * feed pixels to this interface */ -struct dpu_hw_intf_ops { - void (*setup_timing_gen)(struct dpu_hw_intf *intf, - const struct intf_timing_params *p, - const struct dpu_format *fmt); - void (*setup_prg_fetch)(struct dpu_hw_intf *intf, - const struct intf_prog_fetch *fetch); +/* dpu_hw_intf_setup_timing_engine: programs the timing engine */ +void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, + const struct intf_timing_params *p, + const struct dpu_format *fmt); - void (*enable_timing)(struct dpu_hw_intf *intf, - u8 enable); +/* dpu_hw_intf_setup_prg_fetch : enables/disables the programmable fetch logic */ +void dpu_hw_intf_setup_prg_fetch(struct dpu_hw_intf *intf, + const struct intf_prog_fetch *fetch); - void (*get_status)(struct dpu_hw_intf *intf, - struct intf_status *status); +/* dpu_hw_intf_enable_timing_engine: enable/disable timing engine */ +void dpu_hw_intf_enable_timing_engine(struct dpu_hw_intf *intf, + u8 enable); - u32 (*get_line_count)(struct dpu_hw_intf *intf); +/* dpu_hw_intf_get_status: returns if timing engine is enabled or not */ +void dpu_hw_intf_get_status(struct dpu_hw_intf *intf, + struct intf_status *status); - void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, - bool enable, - const enum dpu_pingpong pp); -}; +/* dpu_hw_intf_get_line_count: reads current vertical line counter */ +u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf); + +/* dpu_hw_intf_bind_pingpong_blk: enable/disable the connection with pingpong + * which will feed pixels to this interface */ +void dpu_hw_intf_bind_pingpong_blk(struct dpu_hw_intf *intf, + bool enable, + const enum dpu_pingpong pp); struct dpu_hw_intf { struct dpu_hw_blk base; @@ -84,9 +82,6 @@ struct dpu_hw_intf { enum dpu_intf idx; const struct dpu_intf_cfg *cap; const struct dpu_mdss_cfg *mdss; - - /* ops */ - struct dpu_hw_intf_ops ops; }; /**

[16/21] drm/msm/dpu: call hw_intf ops directly

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