From patchwork Wed Apr 7 14:36:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 12188571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18EABC433B4 for ; Wed, 7 Apr 2021 14:37:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8CB0361260 for ; Wed, 7 Apr 2021 14:37:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8CB0361260 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 02AD46E91E; Wed, 7 Apr 2021 14:37:21 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [1.203.163.78]) by gabe.freedesktop.org (Postfix) with ESMTP id 8E0A06E91E for ; Wed, 7 Apr 2021 14:37:18 +0000 (UTC) X-UUID: 1a14094a131744f9a4ba853018bf1189-20210407 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=HVFoeCxFeSmvJk3GvtJboV3PR4TTvxxrZdUgsEvyBqg=; b=V4t+o36fiY0WTXP3coOXuUG7GP+nBoLdcNi8wzMGnolaZIc/OxcvAtLx/1U6A2deBjDI2qCkfetVEIrG5ltTqvTLGRdew43kBwjq+G3U0jMT/uBWAYYNRl2sZ1yKEk3to+9VS/cAa43/hLHhuSNyAi+E7fXAoN4hmTcVOpwawC8=; X-UUID: 1a14094a131744f9a4ba853018bf1189-20210407 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2036019314; Wed, 07 Apr 2021 22:37:05 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Apr 2021 22:37:02 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 7 Apr 2021 22:37:01 +0800 From: Jitao Shi To: Rob Herring , Mark Rutland , Matthias Brugger , Daniel Vetter , David Airlie , , Subject: [PATCH] drm/mediatek: force hsa hsa hfp packets multiple of line num to avoid screen shift Date: Wed, 7 Apr 2021 22:36:56 +0800 Message-ID: <20210407143656.2574-1-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-TM-SNTS-SMTP: 04143E2A032602C99B68E1021BC15E0AF3D5F349C78BF14AFD651C4F6CAF72E12000:8 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Jitao Shi , srv_heupstream@mediatek.com, huijuan.xie@mediatek.com, stonea168@163.com, cawa.cheng@mediatek.com, rex-bc.chen@mediatek.com, linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The bridge chip ANX7625 require the line packets ending at the sametime or ANX7625 will shift the screen. Change-Id: Ia324ad28fbff54140feedb9a1d6bfb2b246d0447 Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a1ff152ef468..e825a80862de 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk; u32 data_rate; + /* force dsi line end without dsi_null data */ + bool force_dsi_end_without_null; unsigned long mode_flags; enum mipi_dsi_pixel_format format; @@ -495,6 +497,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); } + if (dsi->force_dsi_end_without_null) { + horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2; + horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; + } + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); @@ -1091,6 +1100,9 @@ static int mtk_dsi_probe(struct platform_device *pdev) dsi->bridge.of_node = dev->of_node; dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; + dsi->force_dsi_end_without_null = of_property_read_bool(dev->of_node, + "force_dsi_end_without_null"); + drm_bridge_add(&dsi->bridge); ret = component_add(&pdev->dev, &mtk_dsi_component_ops);